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https://github.com/Polprzewodnikowy/SummerCart64.git
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102 lines
3.7 KiB
Makefile
102 lines
3.7 KiB
Makefile
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# Icarus Verilog
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#TESTBENCH_EXE = tests/testbench.vvp
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# Verilator
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TESTBENCH_EXE = obj_dir/Vtestbench
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test: riscv-torture/build.ok riscv-isa-sim/build.ok
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bash test.sh
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riscv-torture/build.ok: riscv-torture-rv32.diff
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rm -rf riscv-torture
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git clone https://github.com/ucb-bar/riscv-torture.git riscv-torture
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cd riscv-torture && git checkout 2bc0c42
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cd riscv-torture && patch -p1 < ../riscv-torture-rv32.diff
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cd riscv-torture && patch -p1 < ../riscv-torture-genloop.diff
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cd riscv-torture && ./sbt generator/run && touch build.ok
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riscv-fesvr/build.ok:
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rm -rf riscv-fesvr
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git clone https://github.com/riscv/riscv-fesvr.git riscv-fesvr
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+cd riscv-fesvr && git checkout 1c02bd6 && ./configure && make && touch build.ok
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riscv-isa-sim/build.ok: riscv-fesvr/build.ok
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rm -rf riscv-isa-sim
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git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim
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cd riscv-isa-sim && git checkout 10ae74e
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cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-sbreak.diff
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cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-notrap.diff
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cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
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+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
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batch_size = 1000
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batch_list = $(shell bash -c 'for i in {0..$(shell expr $(batch_size) - 1)}; do printf "%03d\n" $$i; done')
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batch: $(addprefix tests/test_,$(addsuffix .ok,$(batch_list)))
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config.vh: config.py riscv-torture/build.ok
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python3 config.py
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obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v config.vh
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verilator --exe -Wno-fatal -DDEBUGASM --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
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$(MAKE) -C obj_dir -f Vtestbench.mk
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tests/testbench.vvp: testbench.v ../../picorv32.v
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mkdir -p tests
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iverilog -o tests/testbench.vvp testbench.v ../../picorv32.v
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tests/generated.ok: config.vh riscv-torture/build.ok
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mkdir -p tests
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rm -f riscv-torture/output/test_*
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cd riscv-torture && ./sbt 'generator/run -C config/test.config -n $(batch_size)'
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touch tests/generated.ok
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define test_template
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tests/test_$(1).S: tests/generated.ok
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mv riscv-torture/output/test_$(1).S tests/
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touch tests/test_$(1).S
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tests/test_$(1).elf: tests/test_$(1).S
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riscv32-unknown-elf-gcc `sed '/march=/ ! d; s,^// ,-,; y/RVIMC/rvimc/;' config.vh` -ffreestanding -nostdlib \
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-Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
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tests/test_$(1).bin: tests/test_$(1).elf
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riscv32-unknown-elf-objcopy -O binary tests/test_$(1).elf tests/test_$(1).bin
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tests/test_$(1).dmp: tests/test_$(1).elf
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riscv32-unknown-elf-objdump -d tests/test_$(1).elf > tests/test_$(1).dmp
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tests/test_$(1).hex: tests/test_$(1).bin
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python3 ../../firmware/makehex.py tests/test_$(1).bin 4096 > tests/test_$(1).hex
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tests/test_$(1).ref: tests/test_$(1).elf riscv-isa-sim/build.ok
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike tests/test_$(1).elf > tests/test_$(1).ref
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tests/test_$(1).ok: $(TESTBENCH_EXE) tests/test_$(1).hex tests/test_$(1).ref tests/test_$(1).dmp
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$(TESTBENCH_EXE) +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref > tests/test_$(1).out
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grep -q PASSED tests/test_$(1).out || { cat tests/test_$(1).out; false; }
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python3 asmcheck.py tests/test_$(1).out tests/test_$(1).dmp
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mv tests/test_$(1).out tests/test_$(1).ok
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endef
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$(foreach id,$(batch_list),$(eval $(call test_template,$(id))))
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loop:
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date +"%s %Y-%m-%d %H:%M:%S START" >> .looplog
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+set -ex; while true; do \
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rm -rf tests obj_dir config.vh; $(MAKE) batch; \
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date +"%s %Y-%m-%d %H:%M:%S NEXT" >> .looplog; \
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done
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clean:
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rm -rf tests obj_dir
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rm -f config.vh test.S test.elf test.bin
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rm -f test.hex test.ref test.vvp test.vcd
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mrproper: clean
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rm -rf riscv-torture riscv-fesvr riscv-isa-sim
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.PHONY: test batch loop clean mrproper
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