mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-10 11:39:23 +01:00
ff69030643
* isv support + usb/dd improvements * make room for saves * update offset * fixed debug address * idk * exception * ironed out all broken stuff * cleanup * return epc fix * better * more cleanup * even more cleanup * mooore cleanup * fixed printf * no assert * improved docker build, pyft232 instead of pyserial * fixed displaying long message strings description test * just straight cleanup * smallest cleanup * PAL * cpu buffer * n64 bootloader done * super slow usb storage reading implemented * reduced buffer size * usb gets fast * little cleanup * double buffered reads * removed separate event id * ISV in hardware finally * small exception changes * mac testing * py spacing * fsd write, rtc, isv and reset fixes * fixxx * good stopping point * usb fixed? * pretend we have 128 MB sdram * backup * chmod * test * test done * more tests * user rm * help * final fix * updated component values * nice asset names * cic 64dd support * ddipl enable separation * pre DMA rewrite, created dedicated buffer memory space, simplified code * dma rewrite, needs testing * moved xml * dd basics * timing * 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite * added usb read functionality, general cleanup * changed mem addressing * added fpga flash update access * added mcu update * chmod * little cleanup * update format and stuff * fixes * uninitialized fix * small fixes * update fixes * update stuff done * fpga update tested * build time fix * boot fix * test timing * readme test * test 2 * reports * testseet * final * build test * forgot * button and naming * General cleanup And multiline commit message test * Exception screen UI touch ups * display separation and tests beginning * pc software update * pc software done * timing test * delete launch.json * sw fixes * fixed button hole diameter in shell * small cleanup, rpi testing * shell fillet fix, pc rtc printing * added cfg lock mechanism * moved lock to cfg address space * extended ROM and ISV fixes * preliminary sd card support * little sd card cleanup * sd menu fixes * 5 second limit * reduced shell thickness * basic led act blinking * faster sd menu loading * inst cache invalidate * sd card writing is working * SD card CSD and CID registers * wait for previous command * led error codes * fixed cfg_translate_address use * 64dd from sd card working * 64dd speedup and button handling * delayed address latching cycle - might break other builds, needs testing * bootloader improvements * small fixes * return previous cfg when setting new * cache stuff * unfloader debug protocol support * UNFLoader style debug command line support * requirements.txt * shell groove fillet * reset state inside controller * fixed fast PI read, added PI R/W fifo debug info * PI access prioritize * SD clock stop when RX FIFO is more than half full * flash erase method change * CFG error handling, TLOZ MM debug ISV support * CIC5167 support * general fixes * USB unplugged cable handling * turn off led when changing between error/act modes * rtc 2 bit clock stop support * line endings * Revert "line endings" This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb. * PI address debug * readme test * diagram update * diagram background * diagram background * diagram background * updated readme
99 lines
4.5 KiB
Verilog
Generated
99 lines
4.5 KiB
Verilog
Generated
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
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/* Module Version: 5.7 */
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/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll_lattice_generated -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phase_cntl STATIC -fb_mode 1 -lock */
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/* Sat Mar 19 17:10:12 2022 */
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`timescale 1 ns / 1 ps
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module pll_lattice_generated (CLKI, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */;
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input wire CLKI;
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output wire CLKOP;
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output wire CLKOS;
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output wire LOCK;
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wire CLKOS_t;
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wire CLKOP_t;
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wire scuba_vlo;
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
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defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
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defparam PLLInst_0.MRST_ENA = "DISABLED" ;
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defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
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defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
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defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
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defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
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defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS_FPHASE = 2 ;
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defparam PLLInst_0.CLKOS_CPHASE = 5 ;
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defparam PLLInst_0.CLKOP_FPHASE = 0 ;
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defparam PLLInst_0.CLKOP_CPHASE = 4 ;
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defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
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defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
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defparam PLLInst_0.FRACN_DIV = 0 ;
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defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
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defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
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defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
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defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
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defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
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defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
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defparam PLLInst_0.CLKOS3_DIV = 1 ;
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defparam PLLInst_0.CLKOS2_DIV = 1 ;
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defparam PLLInst_0.CLKOS_DIV = 5 ;
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defparam PLLInst_0.CLKOP_DIV = 5 ;
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defparam PLLInst_0.CLKFB_DIV = 2 ;
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defparam PLLInst_0.CLKI_DIV = 1 ;
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defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
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EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
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.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
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.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
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.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
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.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
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.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
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.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
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.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
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.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
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.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
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.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
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.CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
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.PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
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.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
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/* synthesis FREQUENCY_PIN_CLKOS="100.000000" */
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/* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
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/* synthesis FREQUENCY_PIN_CLKI="50.000000" */
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/* synthesis ICP_CURRENT="9" */
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/* synthesis LPF_RESISTOR="72" */;
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assign CLKOS = CLKOS_t;
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assign CLKOP = CLKOP_t;
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// exemplar begin
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 100.000000
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 50.000000
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// exemplar attribute PLLInst_0 ICP_CURRENT 9
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// exemplar attribute PLLInst_0 LPF_RESISTOR 72
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// exemplar end
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endmodule
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