mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 06:19:16 +01:00
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
#ifndef SYS_H__
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#define SYS_H__
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#include <stddef.h>
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#include <stdint.h>
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#define DEFAULT_SAVE_OFFSET (0x03FE0000UL)
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#define DEFAULT_DD_OFFSET (0x03BE0000UL)
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typedef volatile uint8_t io8_t;
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typedef volatile uint32_t io32_t;
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#define RAM_BASE (0x00000000UL)
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#define RAM (*((io32_t *) RAM_BASE))
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#define BOOTLOADER_BASE (0x10000000UL)
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#define BOOTLOADER (*((io32_t *) BOOTLOADER_BASE))
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typedef volatile struct gpio_regs {
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io8_t ODR;
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io8_t IDR;
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io8_t OER;
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io8_t __padding;
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} gpio_regs_t;
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#define GPIO_BASE (0x20000000UL)
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#define GPIO ((gpio_regs_t *) GPIO_BASE)
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typedef volatile struct i2c_regs {
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io32_t SCR;
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io32_t DR;
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} i2c_regs_t;
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#define I2C_BASE (0x30000000UL)
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#define I2C ((i2c_regs_t *) I2C_BASE)
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#define I2C_SCR_START (1 << 0)
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#define I2C_SCR_STOP (1 << 1)
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#define I2C_SCR_MACK (1 << 2)
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#define I2C_SCR_ACK (1 << 3)
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#define I2C_SCR_BUSY (1 << 4)
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#define I2C_ADDR_READ (1 << 0)
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typedef volatile struct usb_regs {
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io32_t SCR;
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io8_t DR;
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io8_t __padding[3];
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} usb_regs_t;
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#define USB_BASE (0x40000000UL)
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#define USB ((usb_regs_t *) USB_BASE)
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#define USB_SCR_RXNE (1 << 0)
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#define USB_SCR_TXE (1 << 1)
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#define USB_SCR_FLUSH_RX (1 << 2)
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#define USB_SCR_FLUSH_TX (1 << 3)
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typedef volatile struct uart_regs {
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io32_t SCR;
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io8_t DR;
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io8_t __padding[3];
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} uart_regs_t;
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#define UART_BASE (0x50000000UL)
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#define UART ((uart_regs_t *) UART_BASE)
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#define UART_SCR_RXNE (1 << 0)
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#define UART_SCR_TXE (1 << 1)
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typedef volatile struct dma_regs {
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io32_t SCR;
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io32_t MADDR;
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io32_t ID_LEN;
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} dma_regs_t;
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#define DMA_BASE (0x60000000UL)
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#define DMA ((dma_regs_t *) DMA_BASE)
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#define DMA_SCR_START (1 << 0)
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#define DMA_SCR_STOP (1 << 1)
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#define DMA_SCR_DIR (1 << 2)
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#define DMA_SCR_BUSY (1 << 3)
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typedef volatile struct cfg_regs {
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io32_t SCR;
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io32_t DD_OFFSET;
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io32_t SAVE_OFFSET;
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io8_t CMD;
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io8_t __padding[3];
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io32_t DATA[3];
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} cfg_regs_t;
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#define CFG_BASE (0x70000000UL)
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#define CFG ((cfg_regs_t *) CFG_BASE)
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#define CFG_SCR_SDRAM_SWITCH (1 << 0)
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#define CFG_SCR_SDRAM_WRITABLE (1 << 1)
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#define CFG_SCR_DD_EN (1 << 2)
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#define CFG_SCR_SRAM_EN (1 << 3)
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#define CFG_SCR_SRAM_BANKED (1 << 4)
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#define CFG_SCR_FLASHRAM_EN (1 << 5)
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#define CFG_SCR_CPU_BUSY (1 << 30)
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#define CFG_SCR_CPU_READY (1 << 31)
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#define SDRAM_BASE (0x80000000UL)
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#define SDRAM (*((io32_t *) SDRAM_BASE))
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#define SDRAM_SIZE (64 * 1024 * 1024)
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typedef volatile struct flashram_regs {
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io32_t SCR;
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io32_t __padding[31];
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io32_t BUFFER[32];
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} flashram_regs_t;
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#define FLASHRAM_BASE (0x90000000UL)
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#define FLASHRAM ((flashram_regs_t *) FLASHRAM_BASE)
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#define FLASHRAM_OPERATION_PENDING (1 << 0)
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#define FLASHRAM_OPERATION_DONE (1 << 1)
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#define FLASHRAM_WRITE_OR_ERASE (1 << 2)
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#define FLASHRAM_SECTOR_OR_ALL (1 << 3)
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#define FLASHRAM_SECTOR_BIT (8)
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#endif
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