mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-04 19:04:15 +01:00
367 lines
7.6 KiB
Verilog
367 lines
7.6 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`timescale 1 ns / 1 ps
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module testbench;
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reg flash_csb = 1;
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reg flash_clk = 0;
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wire flash_io0;
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wire flash_io1;
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wire flash_io2;
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wire flash_io3;
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reg flash_io0_oe = 0;
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reg flash_io1_oe = 0;
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reg flash_io2_oe = 0;
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reg flash_io3_oe = 0;
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reg flash_io0_dout = 0;
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reg flash_io1_dout = 0;
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reg flash_io2_dout = 0;
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reg flash_io3_dout = 0;
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assign flash_io0 = flash_io0_oe ? flash_io0_dout : 1'bz;
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assign flash_io1 = flash_io1_oe ? flash_io1_dout : 1'bz;
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assign flash_io2 = flash_io2_oe ? flash_io2_dout : 1'bz;
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assign flash_io3 = flash_io3_oe ? flash_io3_dout : 1'bz;
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spiflash uut (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(flash_io2),
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.io3(flash_io3)
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);
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localparam [23:0] offset = 24'h100000;
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localparam [31:0] word0 = 32'h 00000093;
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localparam [31:0] word1 = 32'h 00000193;
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reg [7:0] rdata;
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integer errcount = 0;
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task expect;
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input [7:0] data;
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begin
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if (data !== rdata) begin
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$display("ERROR: Got %x (%b) but expected %x (%b).", rdata, rdata, data, data);
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errcount = errcount + 1;
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end
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end
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endtask
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task xfer_begin;
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begin
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#5;
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flash_csb = 0;
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$display("-- BEGIN");
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#5;
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end
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endtask
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task xfer_dummy;
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begin
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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#5;
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flash_clk = 1;
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#5;
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flash_clk = 0;
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#5;
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end
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endtask
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task xfer_end;
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begin
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#5;
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flash_csb = 1;
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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$display("-- END");
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$display("");
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#5;
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end
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endtask
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task xfer_spi;
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input [7:0] data;
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integer i;
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begin
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flash_io0_oe = 1;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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for (i = 0; i < 8; i=i+1) begin
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flash_io0_dout = data[7-i];
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#5;
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flash_clk = 1;
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rdata[7-i] = flash_io1;
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#5;
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flash_clk = 0;
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end
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$display("-- SPI SDR %02x %02x", data, rdata);
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#5;
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end
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endtask
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task xfer_qspi_wr;
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input [7:0] data;
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integer i;
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begin
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flash_io0_oe = 1;
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flash_io1_oe = 1;
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flash_io2_oe = 1;
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flash_io3_oe = 1;
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flash_io0_dout = data[4];
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flash_io1_dout = data[5];
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flash_io2_dout = data[6];
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flash_io3_dout = data[7];
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#5;
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flash_clk = 1;
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#5;
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flash_clk = 0;
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flash_io0_dout = data[0];
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flash_io1_dout = data[1];
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flash_io2_dout = data[2];
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flash_io3_dout = data[3];
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#5;
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flash_clk = 1;
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#5;
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flash_clk = 0;
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$display("-- QSPI SDR %02x --", data);
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#5;
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end
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endtask
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task xfer_qspi_rd;
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integer i;
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begin
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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#5;
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flash_clk = 1;
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rdata[4] = flash_io0;
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rdata[5] = flash_io1;
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rdata[6] = flash_io2;
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rdata[7] = flash_io3;
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#5;
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flash_clk = 0;
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#5;
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flash_clk = 1;
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rdata[0] = flash_io0;
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rdata[1] = flash_io1;
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rdata[2] = flash_io2;
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rdata[3] = flash_io3;
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#5;
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flash_clk = 0;
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$display("-- QSPI SDR -- %02x", rdata);
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#5;
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end
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endtask
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task xfer_qspi_ddr_wr;
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input [7:0] data;
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integer i;
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begin
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flash_io0_oe = 1;
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flash_io1_oe = 1;
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flash_io2_oe = 1;
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flash_io3_oe = 1;
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flash_io0_dout = data[4];
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flash_io1_dout = data[5];
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flash_io2_dout = data[6];
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flash_io3_dout = data[7];
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#5;
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flash_clk = 1;
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flash_io0_dout = data[0];
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flash_io1_dout = data[1];
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flash_io2_dout = data[2];
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flash_io3_dout = data[3];
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#5;
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flash_clk = 0;
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$display("-- QSPI DDR %02x --", data);
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#5;
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end
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endtask
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task xfer_qspi_ddr_rd;
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integer i;
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begin
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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#5;
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flash_clk = 1;
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rdata[4] = flash_io0;
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rdata[5] = flash_io1;
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rdata[6] = flash_io2;
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rdata[7] = flash_io3;
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#5;
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flash_clk = 0;
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rdata[0] = flash_io0;
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rdata[1] = flash_io1;
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rdata[2] = flash_io2;
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rdata[3] = flash_io3;
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$display("-- QSPI DDR -- %02x", rdata);
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#5;
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end
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endtask
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initial begin
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$dumpfile("spiflash_tb.vcd");
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$dumpvars(0, testbench);
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$display("");
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$display("Reset (FFh)");
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xfer_begin;
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xfer_spi(8'h ff);
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xfer_end;
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$display("Power Up (ABh)");
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xfer_begin;
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xfer_spi(8'h ab);
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xfer_end;
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$display("Read Data (03h)");
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xfer_begin;
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xfer_spi(8'h 03);
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xfer_spi(offset[23:16]);
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xfer_spi(offset[15:8]);
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xfer_spi(offset[7:0]);
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xfer_spi(8'h 00); expect(word0[7:0]);
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xfer_spi(8'h 00); expect(word0[15:8]);
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xfer_spi(8'h 00); expect(word0[23:16]);
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xfer_spi(8'h 00); expect(word0[31:24]);
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xfer_spi(8'h 00); expect(word1[7:0]);
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xfer_spi(8'h 00); expect(word1[15:8]);
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xfer_spi(8'h 00); expect(word1[23:16]);
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xfer_spi(8'h 00); expect(word1[31:24]);
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xfer_end;
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$display("Quad I/O Read (EBh)");
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xfer_begin;
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xfer_spi(8'h eb);
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xfer_qspi_wr(offset[23:16]);
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xfer_qspi_wr(offset[15:8]);
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xfer_qspi_wr(offset[7:0]);
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xfer_qspi_wr(8'h a5);
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repeat (8) xfer_dummy;
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xfer_qspi_rd; expect(word0[7:0]);
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xfer_qspi_rd; expect(word0[15:8]);
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xfer_qspi_rd; expect(word0[23:16]);
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xfer_qspi_rd; expect(word0[31:24]);
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xfer_qspi_rd; expect(word1[7:0]);
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xfer_qspi_rd; expect(word1[15:8]);
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xfer_qspi_rd; expect(word1[23:16]);
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xfer_qspi_rd; expect(word1[31:24]);
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xfer_end;
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$display("Continous Quad I/O Read");
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xfer_begin;
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xfer_qspi_wr(offset[23:16]);
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xfer_qspi_wr(offset[15:8]);
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xfer_qspi_wr(offset[7:0]);
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xfer_qspi_wr(8'h ff);
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repeat (8) xfer_dummy;
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xfer_qspi_rd; expect(word0[7:0]);
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xfer_qspi_rd; expect(word0[15:8]);
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xfer_qspi_rd; expect(word0[23:16]);
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xfer_qspi_rd; expect(word0[31:24]);
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xfer_qspi_rd; expect(word1[7:0]);
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xfer_qspi_rd; expect(word1[15:8]);
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xfer_qspi_rd; expect(word1[23:16]);
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xfer_qspi_rd; expect(word1[31:24]);
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xfer_end;
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$display("DDR Quad I/O Read (EDh)");
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xfer_begin;
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xfer_spi(8'h ed);
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xfer_qspi_ddr_wr(offset[23:16]);
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xfer_qspi_ddr_wr(offset[15:8]);
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xfer_qspi_ddr_wr(offset[7:0]);
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xfer_qspi_ddr_wr(8'h a5);
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repeat (8) xfer_dummy;
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xfer_qspi_ddr_rd; expect(word0[7:0]);
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xfer_qspi_ddr_rd; expect(word0[15:8]);
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xfer_qspi_ddr_rd; expect(word0[23:16]);
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xfer_qspi_ddr_rd; expect(word0[31:24]);
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xfer_qspi_ddr_rd; expect(word1[7:0]);
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xfer_qspi_ddr_rd; expect(word1[15:8]);
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xfer_qspi_ddr_rd; expect(word1[23:16]);
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xfer_qspi_ddr_rd; expect(word1[31:24]);
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xfer_end;
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$display("Continous DDR Quad I/O Read");
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xfer_begin;
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xfer_qspi_ddr_wr(offset[23:16]);
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xfer_qspi_ddr_wr(offset[15:8]);
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xfer_qspi_ddr_wr(offset[7:0]);
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xfer_qspi_ddr_wr(8'h ff);
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repeat (8) xfer_dummy;
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xfer_qspi_ddr_rd; expect(word0[7:0]);
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xfer_qspi_ddr_rd; expect(word0[15:8]);
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xfer_qspi_ddr_rd; expect(word0[23:16]);
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xfer_qspi_ddr_rd; expect(word0[31:24]);
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xfer_qspi_ddr_rd; expect(word1[7:0]);
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xfer_qspi_ddr_rd; expect(word1[15:8]);
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xfer_qspi_ddr_rd; expect(word1[23:16]);
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xfer_qspi_ddr_rd; expect(word1[31:24]);
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xfer_end;
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#5;
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if (errcount) begin
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$display("FAIL");
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$stop;
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end else begin
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$display("PASS");
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end
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end
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endmodule
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