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https://github.com/Polprzewodnikowy/SummerCart64.git
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86 lines
3.3 KiB
Makefile
86 lines
3.3 KiB
Makefile
RISCV_TOOLS_DIR = /opt/riscv32imc
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RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
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CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
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CC = $(RISCV_TOOLS_PREFIX)gcc
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SHELL = /bin/bash
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help:
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@echo "Usage: make { loop | verilator | iverilog | spike }"
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loop: riscv-fesvr/build.ok riscv-isa-sim/build.ok obj_dir/Vtestbench
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+set -e; x() { echo "$$*" >&2; "$$@"; }; i=1; j=1; while true; do echo; echo; \
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echo "---------------- $$((i++)) ($$j) ----------------"; \
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x rm -f test.hex test.elf test.c test_ref test.ld output_ref.txt output_sim.txt; \
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x make spike test.hex || { echo SKIP; continue; }; x rm -f output_sim.txt; \
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x obj_dir/Vtestbench | grep -v '$$finish' > output_sim.txt; \
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x diff -u output_ref.txt output_sim.txt; echo OK; ! ((j++)); \
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done
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verilator: test_ref test.hex obj_dir/Vtestbench
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timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
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obj_dir/Vtestbench | grep -v '$$finish' > output_sim.txt
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diff -u output_ref.txt output_sim.txt
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iverilog: test_ref test.hex testbench.vvp
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timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
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vvp -N testbench.vvp > output_sim.txt
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diff -u output_ref.txt output_sim.txt
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spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test_ref test.elf
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timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > output_sim.txt
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diff -u output_ref.txt output_sim.txt
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riscv-fesvr/build.ok:
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rm -rf riscv-fesvr
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git clone https://github.com/riscv/riscv-fesvr.git riscv-fesvr
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+cd riscv-fesvr && git checkout 1c02bd6 && ./configure && make && touch build.ok
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riscv-isa-sim/build.ok: riscv-fesvr/build.ok
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rm -rf riscv-isa-sim
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git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim
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cd riscv-isa-sim && git checkout 10ae74e
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cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim.diff
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cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
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+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
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testbench.vvp: testbench.v ../../picorv32.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v
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verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
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$(MAKE) -C obj_dir -f Vtestbench.mk
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test.hex: test.elf
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
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start.elf: start.S start.ld
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$(CC) -nostdlib -o start.elf start.S -T start.ld
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chmod -x start.elf
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test_ref: test.c
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gcc -m32 -o test_ref -w -Os -I $(CSMITH_INCDIR) test.c
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test.elf: test.c syscalls.c start.S
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sed -e '/SECTIONS/,+1 s/{/{ . = 0x00000000; .start : { *(.text.start) } application_entry_point = 0x00010000;/;' \
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$(RISCV_TOOLS_DIR)/riscv32-unknown-elf/lib/riscv.ld > test.ld
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$(CC) -o test.elf -w -Os -I $(CSMITH_INCDIR) -T test.ld test.c syscalls.c start.S
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chmod -x test.elf
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test.c:
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echo "integer size = 4" > platform.info
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echo "pointer size = 4" >> platform.info
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csmith --no-packed-struct -o test.c
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gawk '/Seed:/ {print$$2,$$3;}' test.c
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clean:
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rm -rf platform.info test.c test.ld test.elf test.hex test_ref obj_dir
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rm -rf testbench.vvp testbench.vcd output_ref.txt output_sim.txt
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mrproper: clean
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rm -rf riscv-fesvr riscv-isa-sim
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.PHONY: help loop verilator iverilog spike clean mrproper
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