mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 23:54:15 +01:00
341 lines
9.7 KiB
Systemverilog
341 lines
9.7 KiB
Systemverilog
interface usb_scb ();
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logic fifo_flush;
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logic reset_pending;
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logic reset_ack;
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logic write_buffer_flush;
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modport controller (
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output fifo_flush,
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input reset_pending,
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output reset_ack,
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output write_buffer_flush
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);
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modport usb (
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input fifo_flush,
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output reset_pending,
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input reset_ack,
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input write_buffer_flush
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);
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endinterface
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module usb_ft1248 (
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input clk,
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input reset,
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usb_scb.usb usb_scb,
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fifo_bus.fifo fifo_bus,
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input usb_pwrsav,
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output logic usb_clk,
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output logic usb_cs,
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input usb_miso,
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inout [7:0] usb_miosi
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);
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logic rx_full;
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logic rx_almost_full;
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logic rx_write;
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logic [7:0] rx_wdata;
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logic tx_empty;
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logic tx_almost_empty;
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logic tx_read;
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logic [7:0] tx_rdata;
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fifo_8kb fifo_8kb_rx_inst (
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.clk(clk),
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.reset(reset || usb_scb.fifo_flush),
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.empty(fifo_bus.rx_empty),
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.almost_empty(fifo_bus.rx_almost_empty),
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.read(fifo_bus.rx_read),
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.rdata(fifo_bus.rx_rdata),
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.full(rx_full),
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.almost_full(rx_almost_full),
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.write(rx_write),
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.wdata(rx_wdata)
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);
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fifo_8kb fifo_8kb_tx_inst (
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.clk(clk),
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.reset(reset || usb_scb.fifo_flush),
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.empty(tx_empty),
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.almost_empty(tx_almost_empty),
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.read(tx_read),
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.rdata(tx_rdata),
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.full(fifo_bus.tx_full),
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.almost_full(fifo_bus.tx_almost_full),
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.write(fifo_bus.tx_write),
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.wdata(fifo_bus.tx_wdata)
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);
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logic [1:0] usb_pwrsav_ff;
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logic [7:0] usb_miosi_out;
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logic usb_oe;
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logic ft_pwrsav;
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logic ft_clk;
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logic ft_cs;
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logic ft_miso;
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logic [7:0] ft_miosi_in;
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logic [7:0] ft_miosi_out;
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logic ft_oe;
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always_ff @(posedge clk) begin
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usb_pwrsav_ff <= {usb_pwrsav_ff[0], usb_pwrsav};
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ft_pwrsav <= usb_pwrsav_ff[1];
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usb_clk <= ft_clk;
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usb_cs <= ft_cs;
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ft_miso <= usb_miso;
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ft_miosi_in <= usb_miosi;
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usb_miosi_out <= ft_miosi_out;
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usb_oe <= ft_oe;
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end
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assign usb_miosi = usb_oe ? usb_miosi_out : 8'hZZ;
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typedef enum bit [2:0] {
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STATE_IDLE,
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STATE_SELECT,
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STATE_COMMAND,
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STATE_STATUS,
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STATE_DATA,
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STATE_DESELECT
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} e_state;
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typedef enum bit [7:0] {
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CMD_WRITE = 8'h00,
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CMD_READ = 8'h40,
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CMD_READ_MODEM_STATUS = 8'h20,
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CMD_WRITE_MODEM_STATUS = 8'h60,
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CMD_WRITE_BUFFER_FLUSH = 8'h08
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} e_cmd;
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e_state state;
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e_state next_state;
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e_cmd cmd;
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e_cmd next_cmd;
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logic [3:0] phase;
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logic last_tx_failed;
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logic reset_reply;
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logic last_reset_status;
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logic [4:0] modem_status_counter;
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logic write_modem_status_pending;
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logic write_buffer_flush_pending;
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always_ff @(posedge clk) begin
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state <= next_state;
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cmd <= next_cmd;
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phase <= {phase[2:0], phase[3]};
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if (state == STATE_IDLE) begin
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phase <= 4'b0100;
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end
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if (reset) begin
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last_tx_failed <= 1'b0;
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usb_scb.reset_pending <= 1'b0;
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last_reset_status <= 1'b0;
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modem_status_counter <= 5'd0;
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write_modem_status_pending <= 1'b0;
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write_buffer_flush_pending <= 1'b0;
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end else begin
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if (usb_scb.reset_ack) begin
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usb_scb.reset_pending <= 1'b0;
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reset_reply <= 1'b1;
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write_modem_status_pending <= 1'b1;
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end
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if (usb_scb.write_buffer_flush) begin
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write_buffer_flush_pending <= 1'b1;
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end
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if (state == STATE_IDLE) begin
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modem_status_counter <= modem_status_counter + 1'd1;
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end
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if ((state == STATE_DATA) && (cmd == CMD_WRITE) && phase[3]) begin
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last_tx_failed <= ft_miso;
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end
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if (!ft_miso && (state == STATE_DATA) && phase[3]) begin
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if (cmd == CMD_READ_MODEM_STATUS) begin
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last_reset_status <= ft_miosi_in[0];
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if (!last_reset_status && ft_miosi_in[0]) begin
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usb_scb.reset_pending <= 1'b1;
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end
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if (last_reset_status && !ft_miosi_in[0]) begin
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reset_reply <= 1'b0;
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write_modem_status_pending <= 1'b1;
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end
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end
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if (cmd == CMD_WRITE_MODEM_STATUS) begin
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write_modem_status_pending <= 1'b0;
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end
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if (cmd == CMD_WRITE_BUFFER_FLUSH) begin
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write_buffer_flush_pending <= 1'b0;
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end
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end
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end
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end
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always_comb begin
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ft_clk = 1'b0;
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ft_cs = 1'b1;
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ft_miosi_out = 8'hFF;
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ft_oe = 1'b0;
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if (state == STATE_SELECT) begin
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ft_cs = 1'b0;
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end
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if (state == STATE_COMMAND) begin
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if (phase[0] || phase[1]) begin
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ft_clk = 1'b1;
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end
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ft_cs = 1'b0;
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ft_miosi_out = cmd;
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ft_oe = 1'b1;
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end
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if (state == STATE_STATUS) begin
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if (phase[0] || phase[1]) begin
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ft_clk = 1'b1;
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end
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ft_cs = 1'b0;
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end
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if (state == STATE_DATA) begin
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if (phase[0] || phase[1]) begin
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ft_clk = 1'b1;
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end
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ft_cs = 1'b0;
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if (cmd == CMD_WRITE) begin
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ft_miosi_out = tx_rdata;
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ft_oe = 1'b1;
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end
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if (cmd == CMD_WRITE_MODEM_STATUS) begin
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ft_miosi_out = {2'b00, reset_reply, 5'b00000};
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ft_oe = 1'b1;
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end
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end
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end
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always_comb begin
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rx_write = 1'b0;
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tx_read = 1'b0;
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rx_wdata = ft_miosi_in;
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if (!ft_miso && phase[3]) begin
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case (state)
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STATE_STATUS: begin
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if (cmd == CMD_WRITE && !last_tx_failed) begin
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tx_read = 1'b1;
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end
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end
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STATE_DATA: begin
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if (cmd == CMD_READ) begin
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rx_write = 1'b1;
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end
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if (cmd == CMD_WRITE && !tx_empty) begin
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tx_read = 1'b1;
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end
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end
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endcase
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end
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end
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always_comb begin
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next_state = state;
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next_cmd = cmd;
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if (reset) begin
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next_state = STATE_IDLE;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (ft_pwrsav) begin
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if (write_modem_status_pending) begin
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next_state = STATE_SELECT;
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next_cmd = CMD_WRITE_MODEM_STATUS;
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end else if (&modem_status_counter) begin
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next_state = STATE_SELECT;
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next_cmd = CMD_READ_MODEM_STATUS;
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end else if (!tx_empty || last_tx_failed) begin
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next_state = STATE_SELECT;
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next_cmd = CMD_WRITE;
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end else if (write_buffer_flush_pending) begin
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next_state = STATE_SELECT;
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next_cmd = CMD_WRITE_BUFFER_FLUSH;
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end else if (!rx_full) begin
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next_state = STATE_SELECT;
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next_cmd = CMD_READ;
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end
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end
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end
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STATE_SELECT: begin
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if (phase[3]) begin
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next_state = STATE_COMMAND;
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end
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end
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STATE_COMMAND: begin
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if (phase[3]) begin
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next_state = STATE_STATUS;
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end
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end
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STATE_STATUS: begin
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if (phase[3]) begin
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if (ft_miso) begin
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next_state = STATE_DESELECT;
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end else begin
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next_state = STATE_DATA;
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end
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end
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end
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STATE_DATA: begin
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if (phase[3]) begin
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if (ft_miso) begin
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next_state = STATE_DESELECT;
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end else if (cmd == CMD_READ) begin
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if (rx_almost_full) begin
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next_state = STATE_DESELECT;
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end
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end else if (cmd == CMD_WRITE) begin
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if (tx_empty) begin
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next_state = STATE_DESELECT;
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end
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end else begin
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next_state = STATE_DESELECT;
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end
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end
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end
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STATE_DESELECT: begin
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if (phase[1]) begin
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next_state = STATE_IDLE;
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end
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end
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default: begin
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next_state = STATE_IDLE;
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end
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endcase
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end
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end
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endmodule
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