mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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208 lines
11 KiB
Plaintext
208 lines
11 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
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# Date created = 23:45:19 July 29, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# SummerCart64_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M08SCE144C8G
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:45:19 JULY 29, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_26 -to i_clk
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set_location_assignment PIN_98 -to io_sdram_dq[0]
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set_location_assignment PIN_97 -to io_sdram_dq[1]
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set_location_assignment PIN_96 -to io_sdram_dq[2]
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set_location_assignment PIN_93 -to io_sdram_dq[3]
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set_location_assignment PIN_92 -to io_sdram_dq[4]
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set_location_assignment PIN_91 -to io_sdram_dq[5]
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set_location_assignment PIN_90 -to io_sdram_dq[6]
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set_location_assignment PIN_89 -to io_sdram_dq[7]
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set_location_assignment PIN_99 -to io_sdram_dq[8]
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set_location_assignment PIN_100 -to io_sdram_dq[9]
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set_location_assignment PIN_101 -to io_sdram_dq[10]
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set_location_assignment PIN_102 -to io_sdram_dq[11]
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set_location_assignment PIN_105 -to io_sdram_dq[12]
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set_location_assignment PIN_106 -to io_sdram_dq[13]
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set_location_assignment PIN_110 -to io_sdram_dq[14]
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set_location_assignment PIN_111 -to io_sdram_dq[15]
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set_location_assignment PIN_79 -to o_sdram_a[0]
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set_location_assignment PIN_78 -to o_sdram_a[1]
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set_location_assignment PIN_77 -to o_sdram_a[2]
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set_location_assignment PIN_76 -to o_sdram_a[3]
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set_location_assignment PIN_61 -to o_sdram_a[4]
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set_location_assignment PIN_62 -to o_sdram_a[5]
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set_location_assignment PIN_64 -to o_sdram_a[6]
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set_location_assignment PIN_65 -to o_sdram_a[7]
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set_location_assignment PIN_66 -to o_sdram_a[8]
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set_location_assignment PIN_69 -to o_sdram_a[9]
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set_location_assignment PIN_80 -to o_sdram_a[10]
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set_location_assignment PIN_70 -to o_sdram_a[11]
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set_location_assignment PIN_74 -to o_sdram_a[12]
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set_location_assignment PIN_84 -to o_sdram_ba[0]
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set_location_assignment PIN_81 -to o_sdram_ba[1]
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set_location_assignment PIN_75 -to o_sdram_clk
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set_location_assignment PIN_85 -to o_sdram_cs
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set_location_assignment PIN_87 -to o_sdram_cas
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set_location_assignment PIN_86 -to o_sdram_ras
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set_location_assignment PIN_88 -to o_sdram_we
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set_location_assignment PIN_114 -to o_sd_clk
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set_location_assignment PIN_118 -to io_sd_cmd
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set_location_assignment PIN_119 -to io_sd_dat[3]
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set_location_assignment PIN_120 -to io_sd_dat[2]
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set_location_assignment PIN_112 -to io_sd_dat[1]
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set_location_assignment PIN_113 -to io_sd_dat[0]
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set_location_assignment PIN_134 -to o_flash_cs
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set_location_assignment PIN_131 -to o_flash_clk
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set_location_assignment PIN_132 -to io_flash_dq[3]
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set_location_assignment PIN_136 -to io_flash_dq[2]
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set_location_assignment PIN_135 -to io_flash_dq[1]
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set_location_assignment PIN_130 -to io_flash_dq[0]
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set_location_assignment PIN_122 -to o_sram_clk
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set_location_assignment PIN_123 -to io_sram_dq[3]
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set_location_assignment PIN_127 -to io_sram_dq[2]
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set_location_assignment PIN_126 -to io_sram_dq[1]
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set_location_assignment PIN_121 -to io_sram_dq[0]
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set_location_assignment PIN_124 -to o_sram_cs
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set_location_assignment PIN_24 -to io_n64_si_dq
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set_location_assignment PIN_25 -to i_n64_nmi
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set_location_assignment PIN_27 -to i_n64_reset
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set_location_assignment PIN_28 -to i_n64_si_clk
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set_location_assignment PIN_46 -to i_n64_pi_aleh
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set_location_assignment PIN_50 -to i_n64_pi_alel
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set_location_assignment PIN_47 -to i_n64_pi_read
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set_location_assignment PIN_48 -to i_n64_pi_write
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set_location_assignment PIN_60 -to io_n64_pi_ad[0]
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set_location_assignment PIN_58 -to io_n64_pi_ad[1]
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set_location_assignment PIN_56 -to io_n64_pi_ad[2]
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set_location_assignment PIN_54 -to io_n64_pi_ad[3]
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set_location_assignment PIN_44 -to io_n64_pi_ad[4]
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set_location_assignment PIN_41 -to io_n64_pi_ad[5]
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set_location_assignment PIN_38 -to io_n64_pi_ad[6]
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set_location_assignment PIN_32 -to io_n64_pi_ad[7]
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set_location_assignment PIN_33 -to io_n64_pi_ad[8]
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set_location_assignment PIN_39 -to io_n64_pi_ad[9]
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set_location_assignment PIN_43 -to io_n64_pi_ad[10]
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set_location_assignment PIN_45 -to io_n64_pi_ad[11]
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set_location_assignment PIN_52 -to io_n64_pi_ad[12]
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set_location_assignment PIN_55 -to io_n64_pi_ad[13]
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set_location_assignment PIN_57 -to io_n64_pi_ad[14]
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set_location_assignment PIN_59 -to io_n64_pi_ad[15]
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set_location_assignment PIN_13 -to i_ftdi_do
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set_location_assignment PIN_14 -to o_ftdi_di
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set_location_assignment PIN_12 -to i_ftdi_clk
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set_location_assignment PIN_15 -to i_ftdi_cs
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to o_sdram_clk
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set_location_assignment PIN_29 -to i_n64_cic_clk
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set_location_assignment PIN_30 -to io_n64_cic_dq
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set_location_assignment PIN_138 -to io_pmod[0]
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set_location_assignment PIN_140 -to io_pmod[1]
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set_location_assignment PIN_141 -to io_pmod[2]
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set_location_assignment PIN_6 -to io_pmod[3]
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set_location_assignment PIN_7 -to io_pmod[4]
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set_location_assignment PIN_8 -to io_pmod[5]
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set_location_assignment PIN_10 -to io_pmod[6]
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set_location_assignment PIN_11 -to io_pmod[7]
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set_location_assignment PIN_22 -to io_rtc_sda
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set_location_assignment PIN_21 -to o_rtc_scl
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set_location_assignment PIN_17 -to o_led
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set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE misc/SignalTapLogicAnalyzer.stp
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_cic_dq
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_cic_clk
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_ftdi_do
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
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set_global_assignment -name SMART_RECOMPILE OFF
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_clk
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_ftdi_clk
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set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name VERILOG_FILE rtl/cart_config.v
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set_global_assignment -name VERILOG_FILE rtl/sdram.v
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set_global_assignment -name VERILOG_FILE rtl/external/wbsdram.v
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set_global_assignment -name VERILOG_FILE rtl/external/qflexpress.v
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set_global_assignment -name VERILOG_FILE rtl/address_decoder.v
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set_global_assignment -name VERILOG_FILE rtl/flash.v
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set_global_assignment -name VERILOG_FILE rtl/n64_pi.v
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set_global_assignment -name VERILOG_FILE rtl/pc.v
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set_global_assignment -name VERILOG_FILE rtl/top.v
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set_global_assignment -name SDC_FILE constraints.sdc
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set_global_assignment -name QIP_FILE rtl/intel/pll/pll.qip
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set_global_assignment -name QIP_FILE rtl/intel/gpio/gpio_ddro.qip
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set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_bus_to_pc.qip
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set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_pc_to_bus.qip
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set_global_assignment -name SIGNALTAP_FILE misc/SignalTapLogicAnalyzer.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name SLD_FILE db/SignalTapLogicAnalyzer_auto_stripped.stp |