SummerCart64/fw/rtl/memory
Mateusz Faderewski 856f6948ab dma rewrite finish
2024-07-21 03:39:10 +02:00
..
dma_scb.sv verilator init 2024-07-07 00:09:03 +02:00
mem_bus.sv [SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19) 2022-11-10 11:46:54 +01:00
memory_arbiter.sv [SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19) 2022-11-10 11:46:54 +01:00
memory_bram.sv [SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19) 2022-11-10 11:46:54 +01:00
memory_dma.sv dma rewrite finish 2024-07-21 03:39:10 +02:00
memory_flash.sv [SC64][FW] Flash: fixed partial page write + handle data mask during write 2024-05-03 17:49:44 +02:00
memory_sdram.sv even more fixes and tests 2024-07-08 17:00:49 +02:00