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47 lines
1.0 KiB
Systemverilog
47 lines
1.0 KiB
Systemverilog
module sd_clk (
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input clk,
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input reset,
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sd_scb.clk sd_scb,
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output logic sd_clk_rising,
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output logic sd_clk_falling,
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output logic sd_clk
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);
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logic [7:0] clock_divider;
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always_ff @(posedge clk) begin
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clock_divider <= clock_divider + 1'd1;
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end
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logic selected_clock;
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always_comb begin
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selected_clock = 1'b0;
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case (sd_scb.clock_mode)
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2'd0: selected_clock = 1'b0;
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2'd1: selected_clock = clock_divider[7];
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2'd2: selected_clock = clock_divider[1];
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2'd3: selected_clock = clock_divider[0];
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endcase
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end
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logic last_selected_clock;
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always_ff @(posedge clk) begin
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last_selected_clock <= selected_clock;
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end
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always_comb begin
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sd_clk_rising = !last_selected_clock && selected_clock;
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sd_clk_falling = last_selected_clock && !selected_clock;
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end
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always_ff @(posedge clk) begin
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sd_clk <= last_selected_clock;
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end
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endmodule
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