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34 lines
694 B
Systemverilog
34 lines
694 B
Systemverilog
module sd_crc_16 (
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input clk,
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input reset,
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input enable,
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input shift,
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input data,
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output logic [15:0] result
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);
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logic crc_inv;
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assign crc_inv = result[15] ^ data;
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always_ff @(posedge clk) begin
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if (reset) begin
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result <= 16'd0;
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end else if (enable) begin
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result <= {
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result[14:12],
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result[11] ^ crc_inv,
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result[10:5],
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result[4] ^ crc_inv,
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result[3:0],
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crc_inv
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};
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end else if (shift) begin
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result <= {result[14:0], 1'b1};
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end
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end
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endmodule
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