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48 lines
1.0 KiB
Systemverilog
48 lines
1.0 KiB
Systemverilog
module fifo_8kb (
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input clk,
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input reset,
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output empty,
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output almost_empty,
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input read,
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output [7:0] rdata,
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output full,
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output almost_full,
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input write,
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input [7:0] wdata,
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output logic [10:0] count
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);
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fifo_8kb_lattice_generated fifo_8kb_lattice_generated_inst (
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.Data(wdata),
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.WrClock(clk),
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.RdClock(clk),
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.WrEn(write),
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.RdEn(read),
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.Reset(reset),
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.RPReset(reset),
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.Q(rdata),
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.Empty(empty),
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.Full(full),
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.AlmostEmpty(almost_empty),
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.AlmostFull(almost_full)
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);
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always_ff @(posedge clk) begin
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if (reset) begin
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count <= 11'd0;
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end else begin
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if (write && read) begin
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count <= count;
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end else if (write) begin
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count <= count + 1'd1;
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end else if (read) begin
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count <= count - 1'd1;
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end
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end
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end
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endmodule
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