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37 lines
743 B
Systemverilog
37 lines
743 B
Systemverilog
package sc64;
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typedef enum bit [2:0] {
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ID_N64_SDRAM,
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ID_N64_BOOTLOADER,
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ID_N64_FLASHRAM,
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ID_N64_DDREGS,
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ID_N64_CFG,
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__ID_N64_END
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} e_n64_id;
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typedef enum bit [3:0] {
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ID_CPU_RAM,
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ID_CPU_BOOTLOADER,
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ID_CPU_GPIO,
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ID_CPU_I2C,
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ID_CPU_USB,
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ID_CPU_UART,
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ID_CPU_DMA,
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ID_CPU_CFG,
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__ID_CPU_END
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} e_cpu_id;
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typedef enum bit [1:0] {
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ID_DMA_USB,
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ID_DMA_SD,
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__ID_DMA_END
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} e_dma_id;
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parameter int CLOCK_FREQUENCY = 32'd100_000_000;
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parameter int UART_BAUD_RATE = 32'd1_000_000;
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parameter bit DEBUG_ENABLED = 1'b0;
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endpackage
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