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https://github.com/Polprzewodnikowy/SummerCart64.git
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92 lines
3.2 KiB
Verilog
92 lines
3.2 KiB
Verilog
module device_arbiter #(
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parameter NUM_CONTROLLERS = 2,
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parameter ADDRESS_WIDTH = 26,
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parameter [3:0] DEVICE_BANK = 4'd0,
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parameter ACK_FIFO_LENGTH = 4
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) (
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input i_clk,
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input i_reset,
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input [(NUM_CONTROLLERS - 1):0] i_request,
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input [(NUM_CONTROLLERS - 1):0] i_write,
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output reg [(NUM_CONTROLLERS - 1):0] o_busy,
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output reg [(NUM_CONTROLLERS - 1):0] o_ack,
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input [((NUM_CONTROLLERS * 4) - 1):0] i_bank,
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input [((NUM_CONTROLLERS * ADDRESS_WIDTH) - 1):0] i_address,
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output reg [((NUM_CONTROLLERS * 32) - 1):0] o_data,
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input [((NUM_CONTROLLERS * 32) - 1):0] i_data,
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output reg o_device_request,
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output reg o_device_write,
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input i_device_busy,
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input i_device_ack,
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output reg [(ADDRESS_WIDTH - 1):0] o_device_address,
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input [31:0] i_device_data,
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output reg [31:0] o_device_data
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);
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localparam FIFO_ADDRESS_WIDTH = $clog2(ACK_FIFO_LENGTH);
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reg [(NUM_CONTROLLERS - 1):0] r_request;
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reg [(NUM_CONTROLLERS - 1):0] r_request_successful;
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reg [(NUM_CONTROLLERS - 1):0] r_ack_fifo_mem [0:(ACK_FIFO_LENGTH - 1)];
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reg [FIFO_ADDRESS_WIDTH:0] r_ack_fifo_wrptr;
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reg [FIFO_ADDRESS_WIDTH:0] r_ack_fifo_rdptr;
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wire w_ack_fifo_wrreq = |(r_request_successful & ~i_write);
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wire w_ack_fifo_rdreq = i_device_ack;
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wire w_empty = r_ack_fifo_wrptr[FIFO_ADDRESS_WIDTH] == r_ack_fifo_rdptr[FIFO_ADDRESS_WIDTH];
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wire w_full_or_empty = r_ack_fifo_wrptr[(FIFO_ADDRESS_WIDTH - 1):0] == r_ack_fifo_rdptr[(FIFO_ADDRESS_WIDTH - 1):0];
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wire w_ack_fifo_full = !w_empty && w_full_or_empty;
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_ack_fifo_wrptr <= {(FIFO_ADDRESS_WIDTH + 1){1'b0}};
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r_ack_fifo_rdptr <= {(FIFO_ADDRESS_WIDTH + 1){1'b0}};
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end else begin
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if (w_ack_fifo_wrreq) begin
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r_ack_fifo_mem[r_ack_fifo_wrptr[(FIFO_ADDRESS_WIDTH - 1):0]] <= r_request_successful & ~i_write;
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r_ack_fifo_wrptr <= r_ack_fifo_wrptr + 1'd1;
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end
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if (w_ack_fifo_rdreq) begin
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r_ack_fifo_rdptr <= r_ack_fifo_rdptr + 1'd1;
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end
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end
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end
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always @(*) begin
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for (integer i = 0; i < NUM_CONTROLLERS; i = i + 1) begin
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r_request[i] = i_request[i] && i_bank[(i * 4) +: 4] == DEVICE_BANK;
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o_busy[i] = r_request[i] && (
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i_device_busy ||
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|(r_request & (({{(NUM_CONTROLLERS - 1){1'b0}}, 1'b1} << i) - 1)) ||
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(!i_write[i] && w_ack_fifo_full)
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);
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end
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r_request_successful = r_request & ~o_busy;
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o_ack = {NUM_CONTROLLERS{i_device_ack}} & r_ack_fifo_mem[r_ack_fifo_rdptr[(FIFO_ADDRESS_WIDTH - 1):0]];
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o_data = {NUM_CONTROLLERS{i_device_data}};
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end
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always @(*) begin
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o_device_request = |r_request;
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o_device_write = 1'b0;
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o_device_address = {ADDRESS_WIDTH{1'b0}};
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o_device_data = 32'h0000_0000;
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for (integer i = (NUM_CONTROLLERS - 1); i >= 0 ; i = i - 1) begin
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if (r_request[i]) begin
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o_device_write = i_write[i];
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o_device_address = i_address[(i * ADDRESS_WIDTH) +: ADDRESS_WIDTH];
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o_device_data = i_data[(i * 32) +: 32];
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end
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end
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end
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endmodule
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