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27 lines
639 B
Verilog
27 lines
639 B
Verilog
module sd_crc_16 (
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input i_clk,
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input i_crc_reset,
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input i_crc_shift,
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input i_crc_input,
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output reg [15:0] o_crc_output
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);
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wire w_crc_inv = o_crc_output[15] ^ i_crc_input;
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always @(posedge i_clk) begin
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if (i_crc_reset) begin
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o_crc_output <= 16'd0;
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end else if (i_crc_shift) begin
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o_crc_output <= {
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o_crc_output[14:12],
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o_crc_output[11] ^ w_crc_inv,
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o_crc_output[10:5],
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o_crc_output[4] ^ w_crc_inv,
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o_crc_output[3:0],
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w_crc_inv
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};
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end
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end
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endmodule
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