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https://github.com/Polprzewodnikowy/SummerCart64.git
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46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
package sc64;
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typedef enum bit [2:0] {
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ID_N64_SDRAM,
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ID_N64_BOOTLOADER,
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ID_N64_FLASHRAM,
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ID_N64_DD,
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ID_N64_CFG,
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__ID_N64_END
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} e_n64_id;
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typedef enum bit [3:0] {
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ID_CPU_RAM,
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ID_CPU_FLASH,
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ID_CPU_GPIO,
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ID_CPU_I2C,
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ID_CPU_USB,
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ID_CPU_UART,
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ID_CPU_DMA,
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ID_CPU_CFG,
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ID_CPU_SDRAM,
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ID_CPU_FLASHRAM,
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ID_CPU_SI,
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ID_CPU_DD,
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__ID_CPU_END
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} e_cpu_id;
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typedef enum bit [1:0] {
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ID_DMA_USB,
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ID_DMA_SD,
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__ID_DMA_END
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} e_dma_id;
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parameter bit [31:0] SC64_VER = 32'h53437632;
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parameter int CLOCK_FREQUENCY = 32'd100_000_000;
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parameter bit [31:0] CPU_RESET_VECTOR = {4'(ID_CPU_FLASH), 28'h0010000};
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parameter int UART_BAUD_RATE = 32'd1_000_000;
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`ifdef DEBUG
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parameter bit CPU_HAS_UART = 1'b1;
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`else
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parameter bit CPU_HAS_UART = 1'b0;
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`endif
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endpackage
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