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23 lines
544 B
Systemverilog
23 lines
544 B
Systemverilog
package sc64;
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typedef enum bit [2:0] {
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ID_N64_SDRAM,
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ID_N64_BOOTLOADER,
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ID_N64_FLASHRAM,
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ID_N64_DD,
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ID_N64_CFG,
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__ID_N64_END
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} e_n64_id;
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parameter bit [31:0] SC64_VER = 32'h53437632;
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parameter int CLOCK_FREQUENCY = 32'd100_000_000;
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parameter int UART_BAUD_RATE = 32'd1_000_000;
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`ifdef DEBUG
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parameter bit CPU_HAS_UART = 1'b1;
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`else
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parameter bit CPU_HAS_UART = 1'b0;
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`endif
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endpackage
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