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https://github.com/Polprzewodnikowy/SummerCart64.git
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72 lines
1.4 KiB
Systemverilog
72 lines
1.4 KiB
Systemverilog
module cpu_soc (
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if_system.sys system_if,
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input [7:0] gpio_i,
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output [7:0] gpio_o,
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output [7:0] gpio_oe,
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output usb_clk,
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output usb_cs,
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input usb_miso,
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inout [3:0] usb_miosi,
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input usb_powered,
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inout i2c_scl,
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inout i2c_sda
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);
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enum bit [3:0] {
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RAM,
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BOOTLOADER,
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GPIO,
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I2C,
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USB,
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__NUM_DEVICES
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} e_address_map;
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if_cpu_bus #(
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.NUM_DEVICES(__NUM_DEVICES)
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) bus (
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.clk(system_if.clk),
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.reset(system_if.reset)
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);
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cpu_wrapper # (
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.ENTRY_DEVICE(BOOTLOADER)
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) cpu_wrapper_inst (
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.bus(bus)
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);
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cpu_ram cpu_ram_inst (
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.bus(bus.at[RAM].device)
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);
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cpu_bootloader cpu_bootloader_inst (
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.bus(bus.at[BOOTLOADER].device)
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);
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cpu_gpio cpu_gpio_inst (
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.bus(bus.at[GPIO].device),
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.gpio_i(gpio_i),
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.gpio_o(gpio_o),
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.gpio_oe(gpio_oe)
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);
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cpu_i2c cpu_i2c_inst (
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.bus(bus.at[I2C].device),
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.i2c_scl(i2c_scl),
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.i2c_sda(i2c_sda)
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);
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cpu_usb cpu_usb_inst (
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.system_if(system_if),
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.bus(bus.at[USB].device),
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.usb_clk(usb_clk),
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.usb_cs(usb_cs),
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.usb_miso(usb_miso),
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.usb_miosi(usb_miosi),
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.usb_powered(usb_powered)
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);
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endmodule
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