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46 lines
813 B
Systemverilog
46 lines
813 B
Systemverilog
interface if_system (input in_clk);
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logic clk;
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logic sdram_clk;
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logic reset;
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modport pll (
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input in_clk,
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output clk,
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output sdram_clk,
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output reset
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);
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modport sys (
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input clk,
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input reset
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);
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modport sdram (
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input sdram_clk
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);
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endinterface
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module system (if_system.pll system_if);
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wire locked;
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wire external_reset;
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assign system_if.reset = ~locked | external_reset;
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intel_pll intel_pll_inst (
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.inclk0(system_if.in_clk),
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.c0(system_if.clk),
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.c1(system_if.sdram_clk),
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.locked(locked)
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);
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// intel_snp intel_snp_inst (
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// .source(external_reset),
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// .source_clk(system_if.clk)
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// );
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endmodule
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