mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-27 16:14:13 +01:00
22 lines
288 B
Systemverilog
22 lines
288 B
Systemverilog
interface sd_scb ();
|
|
|
|
logic [1:0] clock_mode;
|
|
|
|
logic [5:0] index;
|
|
|
|
modport controller (
|
|
output clock_mode,
|
|
|
|
output index
|
|
);
|
|
|
|
modport clk (
|
|
input clock_mode
|
|
);
|
|
|
|
modport cmd (
|
|
input index
|
|
);
|
|
|
|
endinterface
|