mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 15:44:14 +01:00
95 lines
2.5 KiB
Systemverilog
95 lines
2.5 KiB
Systemverilog
module n64_bootloader (
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if_system.sys sys,
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if_n64_bus bus,
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if_config.flash cfg,
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if_flash.flash flash
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);
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typedef enum bit [0:0] {
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S_IDLE,
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S_WAIT
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} e_state;
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typedef enum bit [0:0] {
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T_N64,
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T_CPU
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} e_source_request;
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e_state state;
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e_source_request source_request;
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logic request;
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logic ack;
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logic write;
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logic [31:0] address;
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logic [31:0] wdata;
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logic [31:0] rdata;
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always_ff @(posedge sys.clk) begin
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if (sys.reset) begin
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state <= S_IDLE;
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request <= 1'b0;
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end else begin
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case (state)
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S_IDLE: begin
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if (bus.request || flash.request) begin
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state <= S_WAIT;
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request <= 1'b1;
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if (bus.request) begin
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write <= 1'b0;
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address <= bus.address;
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wdata <= bus.wdata;
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source_request <= T_N64;
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end else if (flash.request) begin
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write <= flash.write;
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address <= flash.address;
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wdata <= flash.wdata;
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source_request <= T_CPU;
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end
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end
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end
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S_WAIT: begin
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if (ack) begin
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state <= S_IDLE;
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request <= 1'b0;
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end
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end
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endcase
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end
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end
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always_comb begin
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bus.ack = source_request == T_N64 && ack;
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bus.rdata = 16'd0;
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if (bus.ack && bus.address < 32'h00010000) begin
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if (bus.address[1]) bus.rdata = {rdata[23:16], rdata[31:24]};
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else bus.rdata = {rdata[7:0], rdata[15:8]};
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end
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flash.ack = source_request == T_CPU && ack;
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flash.rdata = 32'd0;
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if (flash.ack) begin
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flash.rdata = rdata;
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end
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end
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vendor_flash vendor_flash_inst (
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.clk(sys.clk),
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.reset(sys.reset),
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.erase_start(cfg.flash_erase_start),
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.erase_busy(cfg.flash_erase_busy),
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.wp_enable(cfg.flash_wp_enable),
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.wp_disable(cfg.flash_wp_disable),
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.request(request),
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.ack(ack),
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.write(write),
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.address(address),
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.wdata(wdata),
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.rdata(rdata)
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);
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endmodule
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