mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 07:06:52 +01:00
362 lines
9.2 KiB
C
362 lines
9.2 KiB
C
// Original code sourced from https://github.com/jago85/UltraCIC_C
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// MIT License
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// Copyright (c) 2019 Jan Goldacker
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// Copyright (c) 2022-2023 Mateusz Faderewski
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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typedef struct {
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volatile uint32_t CIC_CONFIG[2];
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volatile uint32_t GPIO;
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} ext_regs_t;
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#define EXT ((ext_regs_t *) (0xC0000000UL))
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#define CIC_DQ (1 << 0)
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#define CIC_CLK (1 << 1)
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#define CIC_RESET (1 << 2)
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#define CIC_INVALID_REGION (1 << 3)
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#define CIC_IS_RUNNING() (EXT->GPIO & CIC_RESET)
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#define CIC_CLK_WAIT_LOW() { while ((EXT->GPIO & (CIC_RESET | CIC_CLK)) == (CIC_RESET | CIC_CLK)); }
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#define CIC_CLK_WAIT_HIGH() { while ((EXT->GPIO & (CIC_RESET | CIC_CLK)) == CIC_RESET); }
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#define CIC_DQ_GET() (EXT->GPIO & CIC_DQ)
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#define CIC_DQ_SET(v) { EXT->GPIO = ((v) ? CIC_DQ : 0); }
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#define CIC_CLK_GET() (EXT->GPIO & (CIC_RESET | CIC_CLK))
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#define CIC_NOTIFY_INVALID_REGION() { EXT->GPIO = (CIC_INVALID_REGION | CIC_DQ); }
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typedef struct {
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bool cic_disabled;
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bool cic_64dd_mode;
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bool cic_region;
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uint8_t cic_seed;
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uint8_t cic_checksum[6];
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} cic_config_t;
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static cic_config_t config;
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static uint8_t cic_ram[32];
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static uint8_t cic_x105_ram[30];
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static const uint8_t cic_ram_init[2][32] = {{
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0xE, 0x0, 0x9, 0xA, 0x1, 0x8, 0x5, 0xA, 0x1, 0x3, 0xE, 0x1, 0x0, 0xD, 0xE, 0xC,
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0x0, 0xB, 0x1, 0x4, 0xF, 0x8, 0xB, 0x5, 0x7, 0xC, 0xD, 0x6, 0x1, 0xE, 0x9, 0x8
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}, {
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0xE, 0x0, 0x4, 0xF, 0x5, 0x1, 0x2, 0x1, 0x7, 0x1, 0x9, 0x8, 0x5, 0x7, 0x5, 0xA,
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0x0, 0xB, 0x1, 0x2, 0x3, 0xF, 0x8, 0x2, 0x7, 0x1, 0x9, 0x8, 0x1, 0x1, 0x5, 0xC
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}};
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static void cic_die (void) {
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while (CIC_IS_RUNNING());
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}
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static void cic_init (void) {
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CIC_DQ_SET(1);
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while (!CIC_IS_RUNNING());
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uint32_t cic_config[2];
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cic_config[0] = EXT->CIC_CONFIG[0];
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cic_config[1] = EXT->CIC_CONFIG[1];
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config.cic_disabled = (cic_config[0] & (1 << 26));
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config.cic_64dd_mode = (cic_config[0] & (1 << 25));
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config.cic_region = (cic_config[0] & (1 << 24));
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config.cic_seed = ((cic_config[0] >> 16) & 0xFF);
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config.cic_checksum[0] = ((cic_config[0] >> 8) & 0xFF);
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config.cic_checksum[1] = (cic_config[0] & 0xFF);
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config.cic_checksum[2] = ((cic_config[1] >> 24) & 0xFF);
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config.cic_checksum[3] = ((cic_config[1] >> 16) & 0xFF);
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config.cic_checksum[4] = ((cic_config[1] >> 8) & 0xFF);
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config.cic_checksum[5] = (cic_config[1] & 0xFF);
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if (config.cic_disabled) {
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cic_die();
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}
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}
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static uint8_t cic_read (void) {
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uint8_t value;
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CIC_CLK_WAIT_LOW();
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value = CIC_DQ_GET() ? 1 : 0;
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CIC_CLK_WAIT_HIGH();
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return value;
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}
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static void cic_write (uint8_t value) {
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CIC_CLK_WAIT_LOW();
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CIC_DQ_SET(value);
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CIC_CLK_WAIT_HIGH();
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CIC_DQ_SET(1);
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}
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static uint8_t cic_read_nibble (void) {
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uint8_t data = 0;
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for (int i = 0; i < 4; i++) {
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data = ((data << 1) | cic_read());
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}
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return data;
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}
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static void cic_write_nibble (uint8_t data) {
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cic_write(data & 0x08);
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cic_write(data & 0x04);
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cic_write(data & 0x02);
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cic_write(data & 0x01);
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}
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static void cic_write_ram_nibbles (uint8_t index) {
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do {
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cic_write_nibble(cic_ram[index++]);
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} while ((index & 0x0F) != 0);
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}
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static void cic_encode_round (uint8_t index) {
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uint8_t data = cic_ram[index++];
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do {
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data = ((((data + 1) & 0x0F) + cic_ram[index]) & 0x0F);
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cic_ram[index++] = data;
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} while ((index & 0x0F) != 0);
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}
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static void cic_write_id (void) {
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if (config.cic_64dd_mode) {
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CIC_CLK_WAIT_LOW();
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while (CIC_CLK_GET() == CIC_RESET) {
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if (!CIC_DQ_GET()) {
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cic_die();
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}
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}
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} else {
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cic_write(0);
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}
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cic_write(config.cic_region ? 1 : 0);
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cic_write(0);
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cic_write(1);
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}
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static void cic_write_seed (void) {
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cic_ram[0x0A] = 0x0B;
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cic_ram[0x0B] = 0x05;
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cic_ram[0x0C] = (config.cic_seed >> 4);
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cic_ram[0x0D] = config.cic_seed;
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cic_ram[0x0E] = (config.cic_seed >> 4);
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cic_ram[0x0F] = config.cic_seed;
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cic_encode_round(0x0A);
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cic_encode_round(0x0A);
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uint32_t timeout = 10000;
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do {
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if (timeout == 0) {
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CIC_NOTIFY_INVALID_REGION();
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cic_die();
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}
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} while (timeout-- && (CIC_CLK_GET() == (CIC_RESET | CIC_CLK)));
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cic_write_ram_nibbles(0x0A);
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}
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static void cic_write_checksum (void) {
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for (int i = 0; i < 4; i++) {
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cic_ram[i] = 0x00;
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}
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for (int i = 0; i < 6; i++) {
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cic_ram[(i * 2) + 4] = ((config.cic_checksum[i] >> 4) & 0x0F);
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cic_ram[(i * 2) + 5] = (config.cic_checksum[i] & 0x0F);
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}
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cic_encode_round(0x00);
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cic_encode_round(0x00);
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cic_encode_round(0x00);
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cic_encode_round(0x00);
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cic_write(0);
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cic_write_ram_nibbles(0x00);
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}
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static void cic_init_ram (void) {
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for (int i = 0; i < 32; i++) {
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cic_ram[i] = cic_ram_init[config.cic_region ? 1 : 0][i];
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}
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cic_ram[0x01] = cic_read_nibble();
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cic_ram[0x11] = cic_read_nibble();
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}
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static void cic_exchange_bytes (uint8_t *a, uint8_t *b) {
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uint8_t tmp = *a;
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*a = *b;
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*b = tmp;
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}
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static void cic_round (uint8_t *m) {
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uint8_t a, b, x;
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x = m[15];
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a = x;
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do {
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b = 1;
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a += (m[b] + 1);
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m[b] = a;
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b++;
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a += (m[b] + 1);
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cic_exchange_bytes(&a, &m[b]);
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m[b] = ~(m[b]);
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b++;
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a &= 0x0F;
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a += ((m[b] & 0x0F) + 1);
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if (a < 16) {
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cic_exchange_bytes(&a, &m[b]);
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b++;
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}
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a += m[b];
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m[b] = a;
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b++;
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a += m[b];
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cic_exchange_bytes(&a, &m[b]);
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b++;
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a &= 0x0F;
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a += 8;
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if (a < 16) {
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a += m[b];
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}
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cic_exchange_bytes(&a, &m[b]);
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b++;
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do {
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a += (m[b] + 1);
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m[b] = a;
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b++;
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b &= 0x0F;
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} while (b != 0);
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a = (x + 0x0F);
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x = (a & 0x0F);
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} while (x != 0x0F);
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}
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static void cic_compare_mode (void) {
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cic_round(&cic_ram[0x10]);
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cic_round(&cic_ram[0x10]);
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cic_round(&cic_ram[0x10]);
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uint8_t index = (cic_ram[0x17] & 0x0F);
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if (index == 0) {
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index = 1;
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}
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index |= 0x10;
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do {
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cic_read();
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cic_write(cic_ram[index] & 0x01);
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if (config.cic_region) {
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index--;
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} else {
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index++;
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}
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} while (index & 0x0F);
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}
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static void cic_x105_algorithm (void) {
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uint8_t a = 5;
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uint8_t carry = 1;
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for (int i = 0; i < 30; ++i) {
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if (!(cic_x105_ram[i] & 0x01)) {
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a += 8;
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}
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if (!(a & 0x02)) {
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a += 4;
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}
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a = ((a + cic_x105_ram[i]) & 0x0F);
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cic_x105_ram[i] = a;
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if (!carry) {
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a += 7;
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}
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a = ((a + cic_x105_ram[i]) & 0x0F);
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a = (a + cic_x105_ram[i] + carry);
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if (a >= 0x10) {
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carry = 1;
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a -= 0x10;
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} else {
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carry = 0;
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}
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a = (~(a) & 0x0F);
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cic_x105_ram[i] = a;
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}
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}
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static void cic_x105_mode (void) {
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cic_write_nibble(0x0A);
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cic_write_nibble(0x0A);
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for (int i = 0; i < 30; i++) {
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cic_x105_ram[i] = cic_read_nibble();
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}
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cic_x105_algorithm();
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cic_write(0);
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for (int i = 0; i < 30; i++) {
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cic_write_nibble(cic_x105_ram[i]);
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}
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}
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static void cic_soft_reset (void) {
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volatile uint32_t timeout = 119050; // ~500 ms delay, measured on real hardware
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CIC_CLK_WAIT_LOW();
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while ((timeout--) && CIC_IS_RUNNING());
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cic_write(0);
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}
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__attribute__((naked)) void cic_main (void) {
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while (true) {
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cic_init();
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cic_write_id();
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cic_write_seed();
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cic_write_checksum();
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cic_init_ram();
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while (CIC_IS_RUNNING()) {
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uint8_t cmd = 0;
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cmd |= (cic_read() << 1);
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cmd |= cic_read();
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if (cmd == 0) {
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cic_compare_mode();
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} else if (cmd == 2) {
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cic_x105_mode();
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} else if (cmd == 3) {
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cic_soft_reset();
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} else {
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cic_die();
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}
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}
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}
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}
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