mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-10 03:29:23 +01:00
ff69030643
* isv support + usb/dd improvements * make room for saves * update offset * fixed debug address * idk * exception * ironed out all broken stuff * cleanup * return epc fix * better * more cleanup * even more cleanup * mooore cleanup * fixed printf * no assert * improved docker build, pyft232 instead of pyserial * fixed displaying long message strings description test * just straight cleanup * smallest cleanup * PAL * cpu buffer * n64 bootloader done * super slow usb storage reading implemented * reduced buffer size * usb gets fast * little cleanup * double buffered reads * removed separate event id * ISV in hardware finally * small exception changes * mac testing * py spacing * fsd write, rtc, isv and reset fixes * fixxx * good stopping point * usb fixed? * pretend we have 128 MB sdram * backup * chmod * test * test done * more tests * user rm * help * final fix * updated component values * nice asset names * cic 64dd support * ddipl enable separation * pre DMA rewrite, created dedicated buffer memory space, simplified code * dma rewrite, needs testing * moved xml * dd basics * timing * 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite * added usb read functionality, general cleanup * changed mem addressing * added fpga flash update access * added mcu update * chmod * little cleanup * update format and stuff * fixes * uninitialized fix * small fixes * update fixes * update stuff done * fpga update tested * build time fix * boot fix * test timing * readme test * test 2 * reports * testseet * final * build test * forgot * button and naming * General cleanup And multiline commit message test * Exception screen UI touch ups * display separation and tests beginning * pc software update * pc software done * timing test * delete launch.json * sw fixes * fixed button hole diameter in shell * small cleanup, rpi testing * shell fillet fix, pc rtc printing * added cfg lock mechanism * moved lock to cfg address space * extended ROM and ISV fixes * preliminary sd card support * little sd card cleanup * sd menu fixes * 5 second limit * reduced shell thickness * basic led act blinking * faster sd menu loading * inst cache invalidate * sd card writing is working * SD card CSD and CID registers * wait for previous command * led error codes * fixed cfg_translate_address use * 64dd from sd card working * 64dd speedup and button handling * delayed address latching cycle - might break other builds, needs testing * bootloader improvements * small fixes * return previous cfg when setting new * cache stuff * unfloader debug protocol support * UNFLoader style debug command line support * requirements.txt * shell groove fillet * reset state inside controller * fixed fast PI read, added PI R/W fifo debug info * PI access prioritize * SD clock stop when RX FIFO is more than half full * flash erase method change * CFG error handling, TLOZ MM debug ISV support * CIC5167 support * general fixes * USB unplugged cable handling * turn off led when changing between error/act modes * rtc 2 bit clock stop support * line endings * Revert "line endings" This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb. * PI address debug * readme test * diagram update * diagram background * diagram background * diagram background * updated readme
76 lines
2.9 KiB
C
76 lines
2.9 KiB
C
#ifndef VR4300_H__
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#define VR4300_H__
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#define HIT_INVALIDATE_I ((4 << 2) | 0)
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#define HIT_WRITE_BACK_INVALIDATE_D ((5 << 2) | 1)
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#define HIT_WRITE_BACK_D ((6 << 2) | 1)
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#define CACHE_LINE_SIZE_I (32)
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#define CACHE_LINE_SIZE_D (16)
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#define C0_BADVADDR $8
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#define C0_COUNT $9
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#define C0_COMPARE $11
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#define C0_STATUS $12
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#define C0_CAUSE $13
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#define C0_EPC $14
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#define C0_SR_IE (1 << 0)
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#define C0_SR_EXL (1 << 1)
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#define C0_SR_EXR (1 << 2)
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#define C0_SR_KSU0 (1 << 3)
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#define C0_SR_KSU1 (1 << 4)
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#define C0_SR_UX (1 << 5)
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#define C0_SR_SX (1 << 6)
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#define C0_SR_KX (1 << 7)
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#define C0_SR_IM0 (1 << 8)
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#define C0_SR_IM1 (1 << 9)
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#define C0_SR_IM2 (1 << 10)
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#define C0_SR_IM3 (1 << 11)
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#define C0_SR_IM4 (1 << 12)
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#define C0_SR_IM5 (1 << 13)
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#define C0_SR_IM6 (1 << 14)
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#define C0_SR_IM7 (1 << 15)
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#define C0_SR_DS_DE (1 << 16)
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#define C0_SR_DS_CE (1 << 17)
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#define C0_SR_DS_CH (1 << 18)
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#define C0_SR_DS_SR (1 << 20)
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#define C0_SR_DS_TS (1 << 21)
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#define C0_SR_DS_BEV (1 << 22)
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#define C0_SR_DS_ITS (1 << 24)
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#define C0_SR_RE (1 << 25)
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#define C0_SR_FR (1 << 26)
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#define C0_SR_RP (1 << 27)
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#define C0_SR_CU0 (1 << 28)
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#define C0_SR_CU1 (1 << 29)
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#define C0_SR_CU2 (1 << 30)
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#define C0_SR_CU3 (1 << 31)
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#define C0_CR_EC0 (1 << 2)
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#define C0_CR_EC1 (1 << 3)
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#define C0_CR_EC2 (1 << 4)
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#define C0_CR_EC3 (1 << 5)
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#define C0_CR_EC4 (1 << 6)
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#define C0_CR_IP0 (1 << 8)
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#define C0_CR_IP1 (1 << 9)
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#define C0_CR_IP2 (1 << 10)
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#define C0_CR_IP3 (1 << 11)
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#define C0_CR_IP4 (1 << 12)
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#define C0_CR_IP5 (1 << 13)
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#define C0_CR_IP6 (1 << 14)
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#define C0_CR_IP7 (1 << 15)
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#define C0_CR_CE0 (1 << 28)
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#define C0_CR_CE1 (1 << 29)
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#define C0_CR_BD (1 << 31)
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#define C0_CR_EC_MASK (C0_CR_EC4 | C0_CR_EC3 | C0_CR_EC2 | C0_CR_EC1 | C0_CR_EC0)
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#define C0_CR_EC_BIT (2)
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#define C0_CR_IP_MASK (C0_CR_IP7 | C0_CR_IP6 | C0_CR_IP5 | C0_CR_IP4 | C0_CR_IP3 | C0_CR_IP2 | C0_CR_IP1 | C0_CR_IP0)
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#define C0_CR_IP_BIT (8)
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#endif
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