SummerCart64/fw/rtl/cpu/cpu_dma.sv
Polprzewodnikowy 90b211c179 better
2021-08-21 04:35:40 +02:00

29 lines
504 B
Systemverilog

interface if_dma ();
logic request;
logic ack;
logic write;
logic [31:0] address;
logic [15:0] rdata;
logic [15:0] wdata;
modport cpu (
output request,
input ack,
output write,
output address,
input rdata,
output wdata
);
modport memory (
input request,
output ack,
input write,
input address,
output rdata,
input wdata
);
endinterface