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29 lines
504 B
Systemverilog
29 lines
504 B
Systemverilog
interface if_dma ();
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logic request;
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logic ack;
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logic write;
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logic [31:0] address;
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logic [15:0] rdata;
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logic [15:0] wdata;
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modport cpu (
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output request,
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input ack,
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output write,
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output address,
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input rdata,
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output wdata
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);
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modport memory (
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input request,
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output ack,
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input write,
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input address,
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output rdata,
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input wdata
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);
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endinterface
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