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53 lines
1.3 KiB
Systemverilog
53 lines
1.3 KiB
Systemverilog
module n64_sdram (
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if_system sys,
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if_n64_bus bus,
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if_dma.memory dma,
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output sdram_cs,
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output sdram_ras,
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output sdram_cas,
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output sdram_we,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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inout [15:0] sdram_dq
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);
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logic mem_request;
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logic mem_ack;
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logic mem_write;
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logic [31:0] mem_address;
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logic [15:0] mem_rdata;
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logic [15:0] mem_wdata;
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always_comb begin
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mem_request = bus.request || dma.request;
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bus.ack = bus.request && mem_ack;
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dma.ack = dma.request && mem_ack;
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mem_write = (bus.request && bus.write) || (dma.request && dma.write);
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mem_address = dma.request ? dma.address : bus.address;
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mem_wdata = dma.request ? dma.wdata : bus.wdata;
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bus.rdata = mem_rdata;
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dma.rdata = mem_rdata;
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end
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memory_sdram memory_sdram_inst (
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.sys(sys),
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.request(mem_request),
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.ack(mem_ack),
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.write(mem_write),
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.address(mem_address),
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.rdata(mem_rdata),
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.wdata(mem_wdata),
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.sdram_cs(sdram_cs),
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.sdram_ras(sdram_ras),
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.sdram_cas(sdram_cas),
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.sdram_we(sdram_we),
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.sdram_ba(sdram_ba),
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.sdram_a(sdram_a),
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.sdram_dq(sdram_dq)
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);
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endmodule
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