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76 lines
2.2 KiB
Verilog
76 lines
2.2 KiB
Verilog
`include "../constants.vh"
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module n64_bank_decoder (
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input i_clk,
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input i_address_high_op,
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input [15:0] i_n64_pi_ad,
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output reg [3:0] o_bank,
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output reg o_prefetch,
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output reg o_ddipl_pi_request,
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output reg o_sram_pi_request,
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output reg o_flashram_pi_request,
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input i_ddipl_enable,
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input i_sram_enable,
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input i_flashram_enable,
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input i_eeprom_pi_enable,
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input i_sd_enable
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);
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always @(posedge i_clk) begin
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if (i_address_high_op) begin
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o_bank <= `BANK_INVALID;
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o_prefetch <= 1'b1;
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o_ddipl_pi_request <= 1'b0;
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o_sram_pi_request <= 1'b0;
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o_flashram_pi_request <= 1'b0;
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casez (i_n64_pi_ad)
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16'b0000011000??????: begin // DDIPL
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if (i_ddipl_enable) begin
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o_bank <= `BANK_SDRAM;
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o_ddipl_pi_request <= 1'b1;
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end
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end
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16'b000010000000000?: begin // SRAM / FlashRAM
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if (i_flashram_enable) begin
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o_bank <= `BANK_SDRAM;
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o_flashram_pi_request <= 1'b1;
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end else if (i_sram_enable) begin
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o_bank <= `BANK_SDRAM;
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o_sram_pi_request <= 1'b1;
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end
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end
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16'b000100??????????: begin // ROM
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o_bank <= `BANK_SDRAM;
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end
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16'b0001111000000000: begin // CART
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o_bank <= `BANK_CART;
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o_prefetch <= 1'b0;
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end
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16'b0001111000000001: begin // SD
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if (i_sd_enable) begin
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o_bank <= `BANK_SD;
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o_prefetch <= 1'b0;
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end
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end
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16'b0001111000000011: begin // EEPROM
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if (i_eeprom_pi_enable) begin
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o_bank <= `BANK_EEPROM;
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end
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end
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default: begin end
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endcase
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end
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end
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endmodule
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