mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 14:29:14 +01:00
68 lines
1.6 KiB
Systemverilog
68 lines
1.6 KiB
Systemverilog
interface if_n64_bus ();
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localparam sc64::e_n64_id NUM_DEVICES = sc64::__ID_N64_END;
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sc64::e_n64_id id;
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logic request;
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logic ack;
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logic write;
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logic [31:0] address;
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logic [15:0] wdata;
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logic [15:0] rdata;
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logic [31:0] real_address;
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logic read_op;
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logic write_op;
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logic device_ack [(NUM_DEVICES - 1):0];
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logic [15:0] device_rdata [(NUM_DEVICES - 1):0];
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always_comb begin
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ack = 1'b0;
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rdata = 16'd0;
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for (integer i = 0; i < NUM_DEVICES; i++) begin
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ack = ack | device_ack[i];
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rdata = rdata | device_rdata[i];
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end
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end
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modport n64 (
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output id,
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output request,
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input ack,
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output write,
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output address,
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output wdata,
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input rdata,
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output real_address,
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output read_op,
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output write_op
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);
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genvar n;
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generate
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for (n = 0; n < NUM_DEVICES; n++) begin : at
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logic device_request;
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always_comb begin
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device_request = request && id == sc64::e_n64_id'(n);
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end
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modport device (
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input .request(device_request),
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output .ack(device_ack[n]),
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input .write(write),
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input .address(address),
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input .wdata(wdata),
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output .rdata(device_rdata[n]),
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input .real_address(real_address),
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input .read_op(read_op),
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input .write_op(write_op)
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);
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end
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endgenerate
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endinterface
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