mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-30 17:14:14 +01:00
121 lines
3.6 KiB
Verilog
121 lines
3.6 KiB
Verilog
`include "../constants.vh"
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module n64_bank_decoder (
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input i_clk,
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input i_address_high_op,
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input i_address_low_op,
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input [15:0] i_n64_pi_ad,
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output reg [3:0] o_bank,
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output reg o_prefetch,
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output reg o_ddipl_request,
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output reg o_sram_request,
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input i_ddipl_enable,
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input i_sram_enable,
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input i_sram_768k_mode,
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input i_flashram_enable,
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input i_eeprom_enable,
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input i_sd_enable
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);
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reg r_address_high_lsb;
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always @(posedge i_clk) begin
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if (i_address_high_op) begin
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o_bank <= `BANK_INVALID;
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o_prefetch <= 1'b1;
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o_ddipl_request <= 1'b0;
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o_sram_request <= 1'b0;
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casez (i_n64_pi_ad)
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16'b0000011000??????: begin // DDIPL
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if (i_ddipl_enable) begin
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o_bank <= `BANK_SDRAM;
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o_ddipl_request <= 1'b1;
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end
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end
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16'b000010000000000?: begin // SRAM / FlashRAM
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r_address_high_lsb <= i_n64_pi_ad[0];
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if (i_flashram_enable && !i_n64_pi_ad[0]) begin
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o_bank <= `BANK_FLASHRAM;
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end else if (i_sram_enable) begin
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o_bank <= `BANK_SDRAM;
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o_sram_request <= 1'b1;
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end
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end
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16'b000100??????????: begin // ROM
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o_bank <= `BANK_SDRAM;
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end
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16'b0001111000000000: begin // CART
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o_bank <= `BANK_CART;
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o_prefetch <= 1'b0;
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end
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16'b0001111000000001: begin // EEPROM
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if (i_eeprom_enable) begin
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o_bank <= `BANK_EEPROM;
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end
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end
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16'b0001111000000010: begin // SD
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if (i_sd_enable) begin
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o_bank <= `BANK_SD;
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o_prefetch <= 1'b0;
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end
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end
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default: begin end
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endcase
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end
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if (i_address_low_op) begin
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case (o_bank)
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`BANK_SDRAM: begin
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if (o_sram_request) begin
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if (i_sram_768k_mode) begin
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if (r_address_high_lsb && i_n64_pi_ad[1]) begin
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o_bank <= `BANK_INVALID;
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end
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end else begin
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if (i_n64_pi_ad[1]) begin
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o_bank <= `BANK_INVALID;
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end
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end
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end
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end
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`BANK_CART: begin
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if (i_n64_pi_ad[15:14] != 2'b00) begin
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o_bank <= `BANK_INVALID;
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end
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end
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`BANK_EEPROM: begin
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if (i_n64_pi_ad[15:11] != 5'b00000) begin
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o_bank <= `BANK_INVALID;
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end
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end
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`BANK_FLASHRAM: begin
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if (r_address_high_lsb) begin
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o_bank <= `BANK_INVALID;
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end
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end
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`BANK_SD: begin
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if (i_n64_pi_ad[15:10] != 6'b000000) begin
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o_bank <= `BANK_INVALID;
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end
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end
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default: begin end
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endcase
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end
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end
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endmodule
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