mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-27 16:14:13 +01:00
554 lines
16 KiB
Verilog
554 lines
16 KiB
Verilog
`include "constants.vh"
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module top (
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input i_clk,
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output o_ftdi_clk,
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output o_ftdi_si,
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input i_ftdi_so,
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input i_ftdi_cts,
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input i_n64_reset,
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input i_n64_nmi,
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input i_n64_pi_alel,
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input i_n64_pi_aleh,
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input i_n64_pi_read,
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input i_n64_pi_write,
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inout [15:0] io_n64_pi_ad,
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input i_n64_si_clk,
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inout io_n64_si_dq,
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output o_sdram_clk,
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output o_sdram_cs,
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output o_sdram_ras,
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output o_sdram_cas,
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output o_sdram_we,
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output [1:0] o_sdram_ba,
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output [12:0] o_sdram_a,
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inout [15:0] io_sdram_dq,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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output o_sram_clk,
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output o_sram_cs,
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inout [3:0] io_sram_dq,
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output o_rtc_scl,
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inout io_rtc_sda,
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output o_led,
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inout [7:0] io_pmod
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);
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// Clock and reset signals
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wire w_sys_clk;
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wire w_sdram_clk;
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wire w_pll_lock;
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wire w_sys_reset = ~w_pll_lock;
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// Temporary signal names
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wire w_n64_reset_btn;
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assign {o_sram_clk, o_sram_cs, io_sram_dq} = 6'bZZZZZZ;
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assign {o_rtc_scl, io_rtc_sda} = 2'bZZ;
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assign io_pmod[3] = w_n64_reset_btn ? 1'bZ : 1'b0;
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assign {io_pmod[7:4], io_pmod[2:0]} = 7'bZZZZZZZ;
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// PLL clock generator
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pll sys_pll (
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.inclk0(i_clk),
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.c0(w_sys_clk),
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.c1(w_sdram_clk),
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.locked(w_pll_lock)
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);
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// SDRAM clock output
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gpio_ddro sdram_clk_ddro (
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.outclock(w_sdram_clk),
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.outclocken(1'b1),
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.din({1'b0, 1'b1}),
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.pad_out(o_sdram_clk)
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);
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// SD clock output
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wire w_sd_clk;
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gpio_ddro sd_clk_ddro (
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.outclock(w_sd_clk),
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.outclocken(1'b1),
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.din({1'b0, 1'b1}),
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.pad_out(o_sd_clk)
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);
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// N64 PI
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wire w_n64_request;
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wire w_n64_write;
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wire w_n64_busy;
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wire w_n64_ack;
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wire [3:0] w_n64_bank;
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wire [25:0] w_n64_address;
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wire [31:0] w_n64_i_data;
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wire [31:0] w_n64_o_data;
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wire w_n64_busy_cart_control;
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wire w_n64_ack_cart_control;
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wire [31:0] w_n64_i_data_cart_control;
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wire w_n64_busy_sdram;
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wire w_n64_ack_sdram;
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wire [31:0] w_n64_i_data_sdram;
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wire w_n64_busy_embedded_flash;
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wire w_n64_ack_embedded_flash;
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wire [31:0] w_n64_i_data_embedded_flash;
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wire w_n64_busy_eeprom;
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wire w_n64_ack_eeprom;
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wire [31:0] w_n64_i_data_eeprom;
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wire w_n64_busy_sd;
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wire w_n64_ack_sd;
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wire [31:0] w_n64_i_data_sd;
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wire w_sram_request;
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wire w_ddipl_enable;
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wire w_sram_enable;
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wire w_sram_768k_mode;
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wire w_flashram_enable;
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wire w_sd_enable;
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wire w_eeprom_pi_enable;
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wire [23:0] w_ddipl_address;
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wire [23:0] w_sram_address;
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always @(*) begin
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w_n64_busy = w_n64_busy_cart_control || w_n64_busy_sdram || w_n64_busy_embedded_flash || w_n64_busy_eeprom || w_n64_busy_sd;
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w_n64_ack = w_n64_ack_cart_control || w_n64_ack_sdram || w_n64_ack_embedded_flash || w_n64_ack_eeprom || w_n64_ack_sd;
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w_n64_i_data = 32'h0000_0000;
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if (w_n64_ack_cart_control) w_n64_i_data = w_n64_i_data_cart_control;
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if (w_n64_ack_sdram) w_n64_i_data = w_n64_i_data_sdram;
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if (w_n64_ack_embedded_flash) w_n64_i_data = w_n64_i_data_embedded_flash;
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if (w_n64_ack_eeprom) w_n64_i_data = w_n64_i_data_eeprom;
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if (w_n64_ack_sd) w_n64_i_data = w_n64_i_data_sd;
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end
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n64_pi n64_pi_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_n64_reset(i_n64_reset),
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.i_n64_pi_alel(i_n64_pi_alel),
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.i_n64_pi_aleh(i_n64_pi_aleh),
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.i_n64_pi_read(i_n64_pi_read),
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.i_n64_pi_write(i_n64_pi_write),
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.io_n64_pi_ad(io_n64_pi_ad),
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.o_request(w_n64_request),
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.o_write(w_n64_write),
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.i_busy(w_n64_busy),
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.i_ack(w_n64_ack),
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.o_bank(w_n64_bank),
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.o_address(w_n64_address),
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.i_data(w_n64_i_data),
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.o_data(w_n64_o_data),
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.o_sram_request(w_sram_request),
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.i_ddipl_enable(w_ddipl_enable),
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.i_sram_enable(w_sram_enable),
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.i_sram_768k_mode(w_sram_768k_mode),
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.i_flashram_enable(w_flashram_enable),
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.i_sd_enable(w_sd_enable),
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.i_eeprom_enable(w_eeprom_pi_enable),
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.i_ddipl_address(w_ddipl_address),
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.i_sram_address(w_sram_address)
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);
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// PC USB
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wire w_pc_request;
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wire w_pc_write;
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wire w_pc_busy;
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wire w_pc_ack;
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wire [3:0] w_pc_bank;
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wire [25:0] w_pc_address;
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wire [31:0] w_pc_i_data;
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wire [31:0] w_pc_o_data;
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wire w_pc_busy_cart_control;
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wire w_pc_ack_cart_control;
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wire [31:0] w_pc_i_data_cart_control;
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wire w_pc_busy_sdram;
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wire w_pc_ack_sdram;
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wire [31:0] w_pc_i_data_sdram;
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wire w_pc_busy_eeprom;
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wire w_pc_ack_eeprom;
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wire [31:0] w_pc_i_data_eeprom;
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wire w_debug_dma_start;
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wire w_debug_dma_busy;
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wire [3:0] w_debug_dma_bank;
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wire [23:0] w_debug_dma_address;
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wire [19:0] w_debug_dma_length;
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wire w_debug_fifo_request;
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wire w_debug_fifo_flush;
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wire [10:0] w_debug_fifo_items;
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wire [31:0] w_debug_fifo_data;
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always @(*) begin
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w_pc_busy = w_pc_busy_cart_control || w_pc_busy_sdram || w_pc_busy_eeprom;
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w_pc_ack = w_pc_ack_cart_control || w_pc_ack_sdram || w_pc_ack_eeprom;
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w_pc_i_data = 32'h0000_0000;
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if (w_pc_ack_cart_control) w_pc_i_data = w_pc_i_data_cart_control;
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if (w_pc_ack_sdram) w_pc_i_data = w_pc_i_data_sdram;
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if (w_pc_ack_eeprom) w_pc_i_data = w_pc_i_data_eeprom;
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end
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usb_pc #(
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.VERSION(`VERSION)
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) usb_pc_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.o_ftdi_clk(o_ftdi_clk),
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.o_ftdi_si(o_ftdi_si),
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.i_ftdi_so(i_ftdi_so),
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.i_ftdi_cts(i_ftdi_cts),
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.o_request(w_pc_request),
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.o_write(w_pc_write),
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.i_busy(w_pc_busy),
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.i_ack(w_pc_ack),
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.o_bank(w_pc_bank),
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.o_address(w_pc_address),
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.i_data(w_pc_i_data),
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.o_data(w_pc_o_data),
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.i_debug_start(w_debug_dma_start),
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.o_debug_busy(w_debug_dma_busy),
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.i_debug_bank(w_debug_dma_bank),
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.i_debug_address(w_debug_dma_address),
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.i_debug_length(w_debug_dma_length),
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.i_debug_fifo_request(w_debug_fifo_request),
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.i_debug_fifo_flush(w_debug_fifo_flush),
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.o_debug_fifo_items(w_debug_fifo_items),
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.o_debug_fifo_data(w_debug_fifo_data)
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);
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// Cart interface
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wire w_cart_control_request;
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wire w_cart_control_write;
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wire w_cart_control_busy;
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wire w_cart_control_ack;
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wire [10:0] w_cart_control_address;
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wire [31:0] w_cart_control_o_data;
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wire [31:0] w_cart_control_i_data;
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wire w_sdram_writable;
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wire w_rom_switch;
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wire w_eeprom_enable;
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wire w_eeprom_16k_mode;
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device_arbiter #(
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.NUM_CONTROLLERS(2),
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.ADDRESS_WIDTH(11),
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.DEVICE_BANK(`BANK_CART)
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) device_arbiter_cart_control_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request({w_pc_request, w_n64_request}),
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.i_write({w_pc_write, w_n64_write}),
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.o_busy({w_pc_busy_cart_control, w_n64_busy_cart_control}),
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.o_ack({w_pc_ack_cart_control, w_n64_ack_cart_control}),
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.i_bank({w_pc_bank, w_n64_bank}),
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.i_address({w_pc_address[12:2], w_n64_address[12:2]}),
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.o_data({w_pc_i_data_cart_control, w_n64_i_data_cart_control}),
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.i_data({w_pc_o_data, w_n64_o_data}),
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.o_device_request(w_cart_control_request),
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.o_device_write(w_cart_control_write),
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.i_device_busy(w_cart_control_busy),
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.i_device_ack(w_cart_control_ack),
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.o_device_address(w_cart_control_address),
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.i_device_data(w_cart_control_o_data),
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.o_device_data(w_cart_control_i_data)
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);
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cart_control #(
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.VERSION(`VERSION)
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) cart_control_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_n64_reset(i_n64_reset),
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.i_n64_nmi(i_n64_nmi),
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.i_request(w_cart_control_request),
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.i_write(w_cart_control_write),
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.o_busy(w_cart_control_busy),
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.o_ack(w_cart_control_ack),
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.i_address(w_cart_control_address),
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.o_data(w_cart_control_o_data),
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.i_data(w_cart_control_i_data),
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.o_sdram_writable(w_sdram_writable),
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.o_rom_switch(w_rom_switch),
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.o_ddipl_enable(w_ddipl_enable),
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.o_sram_enable(w_sram_enable),
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.o_sram_768k_mode(w_sram_768k_mode),
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.o_flashram_enable(w_flashram_enable),
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.o_sd_enable(w_sd_enable),
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.o_eeprom_pi_enable(w_eeprom_pi_enable),
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.o_eeprom_enable(w_eeprom_enable),
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.o_eeprom_16k_mode(w_eeprom_16k_mode),
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.o_n64_reset_btn(w_n64_reset_btn),
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.i_debug_ready(1'b1),
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.o_debug_dma_start(w_debug_dma_start),
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.i_debug_dma_busy(w_debug_dma_busy),
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.o_debug_dma_bank(w_debug_dma_bank),
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.o_debug_dma_address(w_debug_dma_address),
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.o_debug_dma_length(w_debug_dma_length),
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.o_debug_fifo_request(w_debug_fifo_request),
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.o_debug_fifo_flush(w_debug_fifo_flush),
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.i_debug_fifo_items(w_debug_fifo_items),
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.i_debug_fifo_data(w_debug_fifo_data),
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.o_ddipl_address(w_ddipl_address),
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.o_sram_address(w_sram_address)
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);
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// Embedded flash
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wire w_embedded_flash_request_n64 = w_n64_request && !w_rom_switch && !w_n64_write && w_n64_bank == `BANK_SDRAM;
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memory_embedded_flash memory_embedded_flash_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request(w_embedded_flash_request_n64),
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.o_busy(w_n64_busy_embedded_flash),
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.o_ack(w_n64_ack_embedded_flash),
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.i_address(w_n64_address[20:2]),
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.o_data(w_n64_i_data_embedded_flash)
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);
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// SD card
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wire w_n64_request_sd = w_n64_request && w_n64_bank == `BANK_SD;
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wire w_sd_dma_request;
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wire w_sd_dma_write;
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wire w_sd_dma_busy;
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wire w_sd_dma_ack;
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wire [3:0] w_sd_dma_bank;
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wire [23:0] w_sd_dma_address;
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wire [31:0] w_sd_dma_i_data;
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wire [31:0] w_sd_dma_o_data;
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wire w_sd_dma_busy_sdram;
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wire w_sd_dma_ack_sdram;
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wire [31:0] w_sd_dma_i_data_sdram;
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wire w_sd_dma_busy_eeprom;
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wire w_sd_dma_ack_eeprom;
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wire [31:0] w_sd_dma_i_data_eeprom;
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always @(*) begin
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w_sd_dma_busy = w_sd_dma_busy_sdram || w_sd_dma_busy_eeprom;
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w_sd_dma_ack = w_sd_dma_ack_sdram || w_sd_dma_ack_eeprom;
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w_sd_dma_i_data = 32'h0000_0000;
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if (w_sd_dma_ack_sdram) w_sd_dma_i_data = w_sd_dma_i_data_sdram;
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if (w_sd_dma_ack_eeprom) w_sd_dma_i_data = w_sd_dma_i_data_eeprom;
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end
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sd_interface sd_interface_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.o_sd_clk(w_sd_clk),
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.io_sd_cmd(io_sd_cmd),
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.io_sd_dat(io_sd_dat),
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.i_request(w_n64_request_sd),
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.i_write(w_n64_write),
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.o_busy(w_n64_busy_sd),
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.o_ack(w_n64_ack_sd),
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.i_address({w_n64_address[9], w_n64_address[4:2]}),
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.o_data(w_n64_i_data_sd),
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.i_data(w_n64_o_data),
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.o_dma_request(w_sd_dma_request),
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.o_dma_write(w_sd_dma_write),
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.i_dma_busy(w_sd_dma_busy),
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.i_dma_ack(w_sd_dma_ack),
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.o_dma_bank(w_sd_dma_bank),
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.o_dma_address(w_sd_dma_address),
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.i_dma_data(w_sd_dma_i_data),
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.o_dma_data(w_sd_dma_o_data)
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);
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// SDRAM
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wire w_sdram_request_n64 = w_n64_request && w_rom_switch && (!w_n64_write || (w_n64_write && (w_sdram_writable || w_sram_request)));
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wire w_sdram_request;
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wire w_sdram_write;
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wire w_sdram_busy;
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wire w_sdram_ack;
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wire [24:0] w_sdram_address;
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wire [31:0] w_sdram_o_data;
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wire [31:0] w_sdram_i_data;
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device_arbiter #(
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.NUM_CONTROLLERS(3),
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.ADDRESS_WIDTH(25),
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.DEVICE_BANK(`BANK_SDRAM)
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) device_arbiter_sdram_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request({w_sd_dma_request, w_pc_request, w_sdram_request_n64}),
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.i_write({w_sd_dma_write, w_pc_write, w_n64_write}),
|
|
.o_busy({w_sd_dma_busy_sdram, w_pc_busy_sdram, w_n64_busy_sdram}),
|
|
.o_ack({w_sd_dma_ack_sdram, w_pc_ack_sdram, w_n64_ack_sdram}),
|
|
.i_bank({w_sd_dma_bank, w_pc_bank, w_n64_bank}),
|
|
.i_address({{w_sd_dma_address, 1'b0}, w_pc_address[25:1], w_n64_address[25:1]}),
|
|
.o_data({w_sd_dma_i_data_sdram, w_pc_i_data_sdram, w_n64_i_data_sdram}),
|
|
.i_data({w_sd_dma_o_data, w_pc_o_data, w_n64_o_data}),
|
|
|
|
.o_device_request(w_sdram_request),
|
|
.o_device_write(w_sdram_write),
|
|
.i_device_busy(w_sdram_busy),
|
|
.i_device_ack(w_sdram_ack),
|
|
.o_device_address(w_sdram_address),
|
|
.i_device_data(w_sdram_o_data),
|
|
.o_device_data(w_sdram_i_data)
|
|
);
|
|
|
|
memory_sdram memory_sdram_inst (
|
|
.i_clk(w_sys_clk),
|
|
.i_reset(w_sys_reset),
|
|
|
|
.o_sdram_cs(o_sdram_cs),
|
|
.o_sdram_ras(o_sdram_ras),
|
|
.o_sdram_cas(o_sdram_cas),
|
|
.o_sdram_we(o_sdram_we),
|
|
.o_sdram_ba(o_sdram_ba),
|
|
.o_sdram_a(o_sdram_a),
|
|
.io_sdram_dq(io_sdram_dq),
|
|
|
|
.i_request(w_sdram_request),
|
|
.i_write(w_sdram_write),
|
|
.o_busy(w_sdram_busy),
|
|
.o_ack(w_sdram_ack),
|
|
.i_address(w_sdram_address),
|
|
.o_data(w_sdram_o_data),
|
|
.i_data(w_sdram_i_data)
|
|
);
|
|
|
|
|
|
// EEPROM 4/16k
|
|
|
|
wire w_eeprom_request;
|
|
wire w_eeprom_write;
|
|
wire w_eeprom_busy;
|
|
wire w_eeprom_ack;
|
|
wire [8:0] w_eeprom_address;
|
|
wire [31:0] w_eeprom_o_data;
|
|
wire [31:0] w_eeprom_i_data;
|
|
|
|
device_arbiter #(
|
|
.NUM_CONTROLLERS(3),
|
|
.ADDRESS_WIDTH(9),
|
|
.DEVICE_BANK(`BANK_EEPROM)
|
|
) device_arbiter_eeprom_inst (
|
|
.i_clk(w_sys_clk),
|
|
.i_reset(w_sys_reset),
|
|
|
|
.i_request({w_sd_dma_request, w_pc_request, w_n64_request}),
|
|
.i_write({w_sd_dma_write, w_pc_write, w_n64_write}),
|
|
.o_busy({w_sd_dma_busy_eeprom, w_pc_busy_eeprom, w_n64_busy_eeprom}),
|
|
.o_ack({w_sd_dma_ack_eeprom, w_pc_ack_eeprom, w_n64_ack_eeprom}),
|
|
.i_bank({w_sd_dma_bank, w_pc_bank, w_n64_bank}),
|
|
.i_address({w_sd_dma_address[8:0], w_pc_address[10:2], w_n64_address[10:2]}),
|
|
.o_data({w_sd_dma_i_data_eeprom, w_pc_i_data_eeprom, w_n64_i_data_eeprom}),
|
|
.i_data({w_sd_dma_o_data, w_pc_o_data, w_n64_o_data}),
|
|
|
|
.o_device_request(w_eeprom_request),
|
|
.o_device_write(w_eeprom_write),
|
|
.i_device_busy(w_eeprom_busy),
|
|
.i_device_ack(w_eeprom_ack),
|
|
.o_device_address(w_eeprom_address),
|
|
.i_device_data(w_eeprom_o_data),
|
|
.o_device_data(w_eeprom_i_data)
|
|
);
|
|
|
|
n64_si n64_si_inst (
|
|
.i_clk(w_sys_clk),
|
|
.i_reset(w_sys_reset),
|
|
|
|
.i_n64_reset(i_n64_reset),
|
|
.i_n64_si_clk(i_n64_si_clk),
|
|
.io_n64_si_dq(io_n64_si_dq),
|
|
|
|
.i_request(w_eeprom_request),
|
|
.i_write(w_eeprom_write),
|
|
.o_busy(w_eeprom_busy),
|
|
.o_ack(w_eeprom_ack),
|
|
.i_address(w_eeprom_address),
|
|
.i_data(w_eeprom_i_data),
|
|
.o_data(w_eeprom_o_data),
|
|
|
|
.i_eeprom_enable(w_eeprom_enable),
|
|
.i_eeprom_16k_mode(w_eeprom_16k_mode)
|
|
);
|
|
|
|
|
|
// LED
|
|
|
|
wire w_led_trigger = (w_n64_request && !w_n64_busy) || (w_pc_request && !w_pc_busy) || (w_sd_dma_request && !w_sd_dma_busy);
|
|
|
|
cart_led cart_led_inst (
|
|
.i_clk(w_sys_clk),
|
|
.i_reset(w_sys_reset),
|
|
|
|
.i_trigger(w_led_trigger),
|
|
|
|
.o_led(o_led)
|
|
);
|
|
|
|
endmodule
|