mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 14:29:14 +01:00
82 lines
1.6 KiB
Systemverilog
82 lines
1.6 KiB
Systemverilog
module cpu_soc (
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if_system.sys sys,
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if_config cfg,
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if_dma dma,
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input [7:0] gpio_i,
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output [7:0] gpio_o,
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output [7:0] gpio_oe,
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output i2c_scl,
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inout i2c_sda,
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output usb_clk,
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output usb_cs,
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input usb_miso,
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inout [3:0] usb_miosi,
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input usb_pwren,
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input uart_rxd,
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output uart_txd,
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input uart_cts,
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output uart_rts,
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output sd_clk,
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inout sd_cmd,
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inout [3:0] sd_dat
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);
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if_cpu_bus bus ();
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cpu_wrapper cpu_wrapper_inst (
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.sys(sys),
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.bus(bus)
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);
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cpu_ram cpu_ram_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_RAM].device)
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);
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cpu_bootloader cpu_bootloader_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_BOOTLOADER].device)
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);
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cpu_gpio cpu_gpio_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_GPIO].device),
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.gpio_i(gpio_i),
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.gpio_o(gpio_o),
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.gpio_oe(gpio_oe)
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);
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cpu_i2c cpu_i2c_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_I2C].device),
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.i2c_scl(i2c_scl),
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.i2c_sda(i2c_sda)
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);
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cpu_usb cpu_usb_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_USB].device),
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.dma(dma),
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.usb_clk(usb_clk),
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.usb_cs(usb_cs),
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.usb_miso(usb_miso),
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.usb_miosi(usb_miosi),
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.usb_pwren(usb_pwren)
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);
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cpu_uart cpu_uart_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_CPU_UART].device),
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.uart_rxd(uart_rxd),
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.uart_txd(uart_txd),
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.uart_cts(uart_cts),
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.uart_rts(uart_rts)
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);
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endmodule
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