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35 lines
824 B
Systemverilog
35 lines
824 B
Systemverilog
interface if_config ();
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logic sdram_switch;
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logic sdram_writable;
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logic dd_enabled;
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logic sram_enabled;
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logic flashram_enabled;
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logic flashram_read_mode;
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logic [25:0] dd_offset;
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logic [25:0] save_offset;
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always_comb begin
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sdram_switch = 1'b1;
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sdram_writable = 1'b0;
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dd_enabled = 1'b1;
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sram_enabled = 1'b1;
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flashram_enabled = 1'b1;
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flashram_read_mode = 1'b1;
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dd_offset = 26'h3BE_0000;
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save_offset = 26'h3FE_0000;
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end
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modport pi (
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input sdram_switch,
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input sdram_writable,
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input dd_enabled,
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input sram_enabled,
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input flashram_enabled,
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input flashram_read_mode,
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input dd_offset,
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input save_offset
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);
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endinterface
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