mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-30 01:04:13 +01:00
ff69030643
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec7.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
114 lines
5.5 KiB
Verilog
Generated
114 lines
5.5 KiB
Verilog
Generated
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
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/* Module Version: 1.2 */
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/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n efb_lattice_generated -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 100 -ufm -ufm_ebr 2038 -mem_size 8 -ufm_0 -wb -dev 7000 */
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/* Sun Jul 31 17:59:17 2022 */
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`timescale 1 ns / 1 ps
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module efb_lattice_generated (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i,
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wb_we_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
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input wire wb_clk_i;
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input wire wb_rst_i;
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input wire wb_cyc_i;
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input wire wb_stb_i;
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input wire wb_we_i;
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input wire [7:0] wb_adr_i;
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input wire [7:0] wb_dat_i;
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output wire [7:0] wb_dat_o;
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output wire wb_ack_o;
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output wire wbc_ufm_irq;
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wire scuba_vhi;
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wire scuba_vlo;
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VHI scuba_vhi_inst (.Z(scuba_vhi));
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
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defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
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defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
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defparam EFBInst_0.UFM_INIT_START_PAGE = 2038 ;
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defparam EFBInst_0.UFM_INIT_PAGES = 8 ;
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defparam EFBInst_0.DEV_DENSITY = "7000L" ;
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defparam EFBInst_0.EFB_UFM = "ENABLED" ;
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defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
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defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
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defparam EFBInst_0.TC_ICR_INT = "OFF" ;
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defparam EFBInst_0.TC_OCR_INT = "OFF" ;
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defparam EFBInst_0.TC_OV_INT = "OFF" ;
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defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
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defparam EFBInst_0.TC_RESETN = "ENABLED" ;
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defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
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defparam EFBInst_0.TC_OCR_SET = 32767 ;
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defparam EFBInst_0.TC_TOP_SET = 65535 ;
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defparam EFBInst_0.GSR = "ENABLED" ;
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defparam EFBInst_0.TC_CCLK_SEL = 1 ;
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defparam EFBInst_0.TC_MODE = "CTCM" ;
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defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
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defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
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defparam EFBInst_0.EFB_TC = "DISABLED" ;
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defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
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defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
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defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
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defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
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defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
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defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
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defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
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defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
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defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
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defparam EFBInst_0.SPI_CLK_DIVIDER = 2 ;
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defparam EFBInst_0.SPI_MODE = "MASTER" ;
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defparam EFBInst_0.EFB_SPI = "DISABLED" ;
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defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
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defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
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defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
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defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
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defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
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defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
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defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
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defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
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defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
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defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
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defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
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defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
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defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
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defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
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defparam EFBInst_0.EFB_WB_CLK_FREQ = "100.0" ;
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EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
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.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
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.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
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.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
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.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
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.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
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.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
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.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
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.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
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.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
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.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
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.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
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.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
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.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
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.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
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.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
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.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
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.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
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.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
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.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
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.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
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.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
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.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
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.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
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.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
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.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
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.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
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.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
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.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
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// exemplar begin
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// exemplar end
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endmodule
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