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225 lines
8.0 KiB
Verilog
Vendored
225 lines
8.0 KiB
Verilog
Vendored
module serv_state
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#(parameter RESET_STRATEGY = "MINI",
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parameter [0:0] WITH_CSR = 1,
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parameter [0:0] ALIGN =0,
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parameter [0:0] MDU = 0,
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parameter W = 1
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)
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(
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input wire i_clk,
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input wire i_rst,
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//State
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input wire i_new_irq,
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input wire i_alu_cmp,
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output wire o_init,
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output reg o_cnt_en,
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output wire o_cnt0to3,
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output wire o_cnt12to31,
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output wire o_cnt0,
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output wire o_cnt1,
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output wire o_cnt2,
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output wire o_cnt3,
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output wire o_cnt7,
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output wire o_cnt_done,
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output wire o_bufreg_en,
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output wire o_ctrl_pc_en,
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output reg o_ctrl_jump,
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output wire o_ctrl_trap,
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input wire i_ctrl_misalign,
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input wire i_sh_done,
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input wire i_sh_done_r,
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output wire [1:0] o_mem_bytecnt,
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input wire i_mem_misalign,
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//Control
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input wire i_bne_or_bge,
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input wire i_cond_branch,
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input wire i_dbus_en,
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input wire i_two_stage_op,
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input wire i_branch_op,
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input wire i_shift_op,
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input wire i_sh_right,
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input wire i_slt_or_branch,
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input wire i_e_op,
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input wire i_rd_op,
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//MDU
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input wire i_mdu_op,
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output wire o_mdu_valid,
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//Extension
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input wire i_mdu_ready,
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//External
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output wire o_dbus_cyc,
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input wire i_dbus_ack,
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output wire o_ibus_cyc,
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input wire i_ibus_ack,
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//RF Interface
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output wire o_rf_rreq,
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output wire o_rf_wreq,
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input wire i_rf_ready,
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output wire o_rf_rd_en);
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reg stage_two_req;
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reg init_done;
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wire misalign_trap_sync;
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reg [4:2] o_cnt;
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reg [3:0] cnt_r;
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reg ibus_cyc;
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//Update PC in RUN or TRAP states
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assign o_ctrl_pc_en = o_cnt_en & !o_init;
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assign o_mem_bytecnt = o_cnt[4:3];
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assign o_cnt0to3 = (o_cnt[4:2] == 3'd0);
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assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11));
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assign o_cnt0 = (o_cnt[4:2] == 3'd0) & cnt_r[0];
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assign o_cnt1 = (o_cnt[4:2] == 3'd0) & cnt_r[1];
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assign o_cnt2 = (o_cnt[4:2] == 3'd0) & cnt_r[2];
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assign o_cnt3 = (o_cnt[4:2] == 3'd0) & cnt_r[3];
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assign o_cnt7 = (o_cnt[4:2] == 3'd1) & cnt_r[3];
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//Take branch for jump or branch instructions (opcode == 1x0xx) if
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//a) It's an unconditional branch (opcode[0] == 1)
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//b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true
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//c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false
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//Only valid during the last cycle of INIT, when the branch condition has
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//been calculated.
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wire take_branch = i_branch_op & (!i_cond_branch | (i_alu_cmp^i_bne_or_bge));
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//valid signal for mdu
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assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op;
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//Prepare RF for writes when everything is ready to enter stage two
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// and the first stage didn't cause a misalign exception
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assign o_rf_wreq = !misalign_trap_sync & !o_cnt_en & init_done &
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((i_shift_op & (i_sh_done | !i_sh_right)) |
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i_dbus_ack | (MDU & i_mdu_ready) |
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i_slt_or_branch);
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assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign;
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//Prepare RF for reads when a new instruction is fetched
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// or when stage one caused an exception (rreq implies a write request too)
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assign o_rf_rreq = i_ibus_ack | (stage_two_req & misalign_trap_sync);
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assign o_rf_rd_en = i_rd_op & !o_init;
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/*
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bufreg is used during mem. branch and shift operations
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mem : bufreg is used for dbus address. Shift in data during phase 1.
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Shift out during phase 2 if there was an misalignment exception.
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branch : Shift in during phase 1. Shift out during phase 2
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shift : Shift in during phase 1. Continue shifting between phases (except
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for the first cycle after init). Shift out during phase 2
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*/
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assign o_bufreg_en = (o_cnt_en & (o_init | ((o_ctrl_trap | i_branch_op) & i_two_stage_op))) | (i_shift_op & !stage_two_req & (i_sh_right | i_sh_done_r) & init_done);
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assign o_ibus_cyc = ibus_cyc & !i_rst;
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assign o_init = i_two_stage_op & !i_new_irq & !init_done;
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assign o_cnt_done = (o_cnt[4:2] == 3'b111) & cnt_r[3];
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always @(posedge i_clk) begin
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//ibus_cyc changes on three conditions.
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//1. i_rst is asserted. Together with the async gating above, o_ibus_cyc
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// will be asserted as soon as the reset is released. This is how the
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// first instruction is fetced
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//2. o_cnt_done and o_ctrl_pc_en are asserted. This means that SERV just
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// finished updating the PC, is done with the current instruction and
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// o_ibus_cyc gets asserted to fetch a new instruction
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//3. When i_ibus_ack, a new instruction is fetched and o_ibus_cyc gets
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// deasserted to finish the transaction
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if (i_ibus_ack | o_cnt_done | i_rst)
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ibus_cyc <= o_ctrl_pc_en | i_rst;
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if (o_cnt_done) begin
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init_done <= o_init & !init_done;
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o_ctrl_jump <= o_init & take_branch;
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end
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//Need a strobe for the first cycle in the IDLE state after INIT
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stage_two_req <= o_cnt_done & o_init;
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if (i_rst) begin
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if (RESET_STRATEGY != "NONE") begin
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init_done <= 1'b0;
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o_ctrl_jump <= 1'b0;
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stage_two_req <= 1'b0;
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end
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end
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end
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always @(posedge i_clk) begin
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/*
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Because SERV is 32-bit bit-serial we need a counter than can count 0-31
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to keep track of which bit we are currently processing. o_cnt and cnt_r
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are used together to create such a counter.
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The top three bits (o_cnt) are implemented as a normal counter, but
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instead of the two LSB, cnt_r is a 4-bit shift register which loops 0-3
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When cnt_r[3] is 1, o_cnt will be increased.
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The counting starts when the core is idle and the i_rf_ready signal
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comes in from the RF module by shifting in the i_rf_ready bit as LSB of
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the shift register. Counting is stopped by using o_cnt_done to block the
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bit that was supposed to be shifted into bit 0 of cnt_r.
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There are two benefit of doing the counter this way
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1. We only need to check four bits instead of five when we want to check
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if the counter is at a certain value. For 4-LUT architectures this means
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we only need one LUT instead of two for each comparison.
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2. We don't need a separate enable signal to turn on and off the counter
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between stages, which saves an extra FF and a unique control signal. We
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just need to check if cnt_r is not zero to see if the counter is
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currently running
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*/
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if (W == 4) begin
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if (i_rf_ready) o_cnt_en <= 1; else
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if (o_cnt_done) o_cnt_en <= 0;
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o_cnt <= o_cnt + { 2'b0, o_cnt_en };
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end else if (W == 1) begin
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o_cnt <= o_cnt + {2'd0,cnt_r[3]};
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cnt_r <= {cnt_r[2:0],(cnt_r[3] & !o_cnt_done) | (i_rf_ready & !o_cnt_en)};
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end
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if (i_rst) begin
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if (RESET_STRATEGY != "NONE") begin
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o_cnt <= 3'd0;
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if (W == 1)
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cnt_r <= 4'b0000;
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else if (W == 4)
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o_cnt_en <= 1'b0;
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end
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end
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end
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always @(*)
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if (W == 1)
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o_cnt_en = |cnt_r;
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else if (W == 4)
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cnt_r = 4'b1111;
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assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync);
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generate
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if (WITH_CSR) begin : gen_csr
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reg misalign_trap_sync_r;
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//trap_pending is only guaranteed to have correct value during the
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// last cycle of the init stage
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wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) |
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(i_dbus_en & i_mem_misalign));
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always @(posedge i_clk) begin
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if (i_ibus_ack | o_cnt_done | i_rst)
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misalign_trap_sync_r <= !(i_ibus_ack | i_rst) & ((trap_pending & o_init) | misalign_trap_sync_r);
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end
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assign misalign_trap_sync = misalign_trap_sync_r;
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end else begin : gen_no_csr
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assign misalign_trap_sync = 1'b0;
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end
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endgenerate
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endmodule
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