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48 lines
1.1 KiB
Verilog
48 lines
1.1 KiB
Verilog
module sd_fifo (
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input i_clk,
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input i_reset,
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input i_fifo_flush,
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input i_fifo_push,
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input i_fifo_pop,
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output o_fifo_empty,
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output o_fifo_full,
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output reg o_fifo_underrun,
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output reg o_fifo_overrun,
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output [8:0] o_fifo_items,
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input [31:0] i_fifo_data,
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output [31:0] o_fifo_data
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);
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wire [7:0] w_fifo_items;
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assign o_fifo_items = {o_fifo_full, w_fifo_items};
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fifo_sd fifo_sd_inst (
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.clock(i_clk),
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.sclr(i_reset || i_fifo_flush),
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.wrreq(i_fifo_push),
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.rdreq(i_fifo_pop),
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.empty(o_fifo_empty),
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.full(o_fifo_full),
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.usedw(w_fifo_items),
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.data(i_fifo_data),
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.q(o_fifo_data)
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);
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always @(posedge i_clk) begin
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if (i_reset || i_fifo_flush) begin
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o_fifo_underrun <= 1'b0;
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o_fifo_overrun <= 1'b0;
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end else begin
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if (o_fifo_empty && i_fifo_pop) begin
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o_fifo_underrun <= 1'b1;
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end
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if (o_fifo_full && i_fifo_push) begin
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o_fifo_overrun <= 1'b1;
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end
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end
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end
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endmodule
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