mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 14:09:16 +01:00
5b85b0f661
* [SC64][SW] Added board bring-up via UART header * [SC64][SW] Made I2C in primer stable * [SC64][SW] LCMXO2 primer fixes * [SC64][SW] SC64 primer PC software * [SC64][SW] Added primer.py to release package * [SC64][SW] Fixed FPGA refresh * [SC64][SW] Changed release package contents
69 lines
1.6 KiB
Plaintext
69 lines
1.6 KiB
Plaintext
MEMORY {
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framebuffer (rw) : org = 0x8026A000, len = 600k
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ram (rwx) : org = 0x80300000, len = 1M
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rom (r) : org = 0xB0000000, len = 1028k
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}
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ENTRY(entry_handler)
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__exception_stack_size = 8k;
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__stack_size = 16k;
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__bootloader_start = ORIGIN(ram);
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__bootloader_size = LENGTH(ram);
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__bootloader_end = __bootloader_start + __bootloader_size;
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SECTIONS {
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.boot : {
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KEEP(*(.text.rom_header));
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KEEP(*(.text.ipl3));
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} > rom
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.framebuffer (NOLOAD) : SUBALIGN(64) {
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*(.framebuffer .framebuffer.*)
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} > framebuffer
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.text : SUBALIGN(4) {
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*(.text.entry_handler)
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*(.text .text.* .gnu.linkonce.t.*)
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*(.assets .assets.*)
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.data .data.* .gnu.linkonce.d.*)
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_gp = . + 0x8000;
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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*(.lit8 .lit4)
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} > ram AT > rom
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.bss : {
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. = ALIGN(8);
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_sbss = .;
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon .scommon.*)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(8);
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_ebss = .;
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} > ram
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_sheap = .;
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. = ORIGIN(ram) + LENGTH(ram) - __exception_stack_size - __stack_size;
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_eheap = .;
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. += __exception_stack_size;
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_esp = .;
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. += __stack_size;
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_sp = .;
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.fill : {
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. = ALIGN(1024) - 4;
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LONG(0xDEADBEEF);
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FILL(0xFFFFFFFF);
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. = ORIGIN(rom) + LENGTH(rom);
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} > rom
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/DISCARD/ : {
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*(.MIPS.*)
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}
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}
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