mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
235 lines
8.6 KiB
Systemverilog
235 lines
8.6 KiB
Systemverilog
module n64_dd (
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input clk,
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input reset,
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n64_reg_bus.dd reg_bus,
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n64_scb.dd n64_scb,
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output logic irq
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);
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const bit [10:0] M_C2_BUFFER = 11'h000;
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const bit [10:0] M_SECTOR_BUFFER = 11'h400;
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typedef enum bit [10:0] {
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R_DATA = 11'h500,
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R_CMD_SR = 11'h508,
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R_TRK_CUR = 11'h50C,
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R_BM_SCR = 11'h510,
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R_RESET = 11'h520,
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R_SEC_SIZ = 11'h528,
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R_SEC_INFO = 11'h530,
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R_ID = 11'h540
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} e_reg_id;
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typedef enum bit [3:0] {
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BM_CONTROL_START_BUFFER_MANAGER = 4'd15,
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BM_CONTROL_BUFFER_MANAGER_MODE = 4'd14,
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BM_CONTROL_BUFFER_MANAGER_RESET = 4'd12,
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BM_CONTROL_BLOCK_TRANSFER = 4'd9,
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BM_CONTROL_MECHANIC_INTERRUPT_RESET = 4'd8
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} e_bm_control_id;
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// typedef enum bit [0:0] {
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// S_IDLE,
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// S_WAIT
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// } e_state;
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// e_state state;
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// always_comb begin
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// dd.sector_address = bus.address[7:1];
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// dd.sector_address_valid = bus.request && bus.address[11:8] == M_SECTOR_BUFFER[11:8];
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// dd.sector_write = bus.write && dd.sector_address_valid;
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// dd.sector_wdata = bus.wdata;
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// end
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always_comb begin
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bus.rdata = 16'd0;
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if (bus.ack) begin
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if (bus.address[10:8] == M_SECTOR_BUFFER[10:8]) begin
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if (bus.address[1]) begin
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bus.rdata = dd.sector_rdata[15:0];
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end else begin
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bus.rdata = dd.sector_rdata[31:16];
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end
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end else begin
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case (bus.address[10:0])
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R_DATA: bus.rdata = dd.data;
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R_CMD_SR: bus.rdata = {
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1'b0,
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dd.bm_transfer_data,
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1'b0,
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dd.bm_transfer_c2,
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1'b0,
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dd.bm_interrupt,
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dd.cmd_interrupt,
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dd.disk_inserted,
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dd.cmd_pending,
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dd.hard_reset,
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1'b0,
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1'b0,
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1'b0,
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1'b0,
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1'b0,
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dd.disk_changed
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};
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R_TRK_CUR: bus.rdata = {1'd0, {2{dd.index_lock}}, dd.head_track};
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R_BM_SCR: bus.rdata = {6'd0, dd.bm_micro_error, 9'd0};
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R_ID: bus.rdata = {dd.drive_id};
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default: bus.rdata = 16'd0;
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endcase
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end
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end
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end
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always_comb begin
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reg_bus.rdata = 16'd0;
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if (reg_bus.address[10:8] == M_SECTOR_BUFFER[10:8]) begin
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end else begin
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case (reg_bus.address[10:0])
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R_DATA: reg_bus.rdata = dd.data;
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R_CMD_SR: reg_bus.rdata = {
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1'b0,
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dd.bm_transfer_data,
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1'b0,
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dd.bm_transfer_c2,
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1'b0,
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dd.bm_interrupt,
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dd.cmd_interrupt,
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dd.disk_inserted,
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dd.cmd_pending,
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dd.hard_reset,
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1'b0,
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1'b0,
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1'b0,
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1'b0,
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1'b0,
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dd.disk_changed
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};
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R_TRK_CUR: reg_bus.rdata = {1'd0, {2{dd.index_lock}}, dd.head_track};
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R_BM_SCR: reg_bus.rdata = {6'd0, dd.bm_micro_error, 9'd0};
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R_ID: reg_bus.rdata = {dd.drive_id};
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default: reg_bus.rdata = 16'd0;
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endcase
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end
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end
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always_ff @(posedge sys.clk) begin
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bus.ack <= 1'b0;
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dd.bm_interrupt_ack <= 1'b0;
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if (dd.hard_reset_clear) begin
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dd.hard_reset <= 1'b0;
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end
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if (dd.cmd_ready) begin
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dd.data <= dd.cmd_data;
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dd.cmd_pending <= 1'b0;
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dd.cmd_interrupt <= 1'b1;
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end
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if (dd.bm_start_clear) begin
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dd.bm_start_pending <= 1'b0;
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end
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if (dd.bm_stop_clear) begin
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dd.bm_stop_pending <= 1'b0;
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end
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if (dd.bm_clear) begin
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dd.bm_pending <= 1'b0;
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end
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if (dd.bm_ready) begin
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dd.bm_interrupt <= 1'b1;
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end
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if (bus.real_address == (M_C2_BUFFER + ({dd.sector_size[7:1], 1'b0} * 3'd4)) && bus.read_op) begin
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dd.bm_pending <= 1'b1;
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end
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if (bus.real_address == (M_SECTOR_BUFFER + {dd.sector_size[7:1], 1'b0}) && (bus.read_op || bus.write_op)) begin
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dd.bm_pending <= 1'b1;
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end
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if (bus.real_address == (M_BASE + R_CMD_SR) && bus.read_op) begin
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dd.bm_interrupt <= 1'b0;
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dd.bm_interrupt_ack <= 1'b1;
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end
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if (sys.reset || sys.n64_hard_reset) begin
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dd.hard_reset <= 1'b1;
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dd.cmd_pending <= 1'b0;
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dd.cmd_interrupt <= 1'b0;
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dd.bm_start_pending <= 1'b0;
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dd.bm_stop_pending <= 1'b0;
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dd.bm_pending <= 1'b0;
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dd.bm_interrupt <= 1'b0;
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state <= S_IDLE;
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end else begin
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case (state)
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S_IDLE: begin
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if (bus.request) begin
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state <= S_WAIT;
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bus.ack <= 1'b1;
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if (bus.write) begin
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case (bus.address[10:0])
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R_DATA: begin
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dd.data <= bus.wdata;
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end
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R_CMD_SR: begin
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dd.cmd <= bus.wdata[7:0];
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dd.cmd_pending <= 1'b1;
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end
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R_BM_SCR: begin
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dd.sector_num <= bus.wdata[7:0];
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if (bus.wdata[BM_CONTROL_START_BUFFER_MANAGER]) begin
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dd.bm_start_pending <= 1'b1;
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dd.bm_stop_pending <= 1'b0;
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dd.bm_transfer_mode <= bus.wdata[BM_CONTROL_BUFFER_MANAGER_MODE];
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dd.bm_transfer_blocks <= bus.wdata[BM_CONTROL_BLOCK_TRANSFER];
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end
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if (bus.wdata[BM_CONTROL_BUFFER_MANAGER_RESET]) begin
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dd.bm_start_pending <= 1'b0;
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dd.bm_stop_pending <= 1'b1;
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dd.bm_transfer_mode <= 1'b0;
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dd.bm_transfer_blocks <= 1'b0;
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dd.bm_pending <= 1'b0;
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dd.bm_interrupt <= 1'b0;
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end
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if (bus.wdata[BM_CONTROL_MECHANIC_INTERRUPT_RESET]) begin
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dd.cmd_interrupt <= 1'b0;
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end
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end
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R_RESET: begin
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if (bus.wdata == 16'hAAAA) begin
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dd.hard_reset <= 1'b1;
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dd.cmd_pending <= 1'b0;
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dd.cmd_interrupt <= 1'b0;
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dd.bm_start_pending <= 1'b0;
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dd.bm_stop_pending <= 1'b0;
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dd.bm_pending <= 1'b0;
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dd.bm_interrupt <= 1'b0;
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end
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end
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R_SEC_SIZ: begin
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dd.sector_size <= bus.wdata[7:0];
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end
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R_SEC_INFO: begin
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dd.sectors_in_block <= bus.wdata[15:8];
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dd.sector_size_full <= bus.wdata[7:0];
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end
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endcase
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end
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end
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end
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S_WAIT: begin
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state <= S_IDLE;
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end
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endcase
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end
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end
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endmodule
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