SummerCart64/fw/cpu/bootloader/cpu_bootloader_template.sv
Polprzewodnikowy b1826a9167 goot
2021-08-23 22:30:47 +02:00

24 lines
470 B
Systemverilog

bus.rdata
module cpu_bootloader (
if_system.sys sys,
if_cpu_bus bus
);
always_ff @(posedge sys.clk) begin
bus.ack <= 1'b0;
if (bus.request) begin
bus.ack <= 1'b1;
end
end
always_comb begin
bus.rdata = 32'd0;
if (bus.ack) begin
case (bus.address[6:2]){rom_formatted}
default: bus.rdata = 32'd0;
endcase
end
end
endmodule