mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 15:44:14 +01:00
62 lines
1.4 KiB
Systemverilog
62 lines
1.4 KiB
Systemverilog
interface if_config ();
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logic cpu_bootstrapped;
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logic cpu_busy;
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logic request;
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logic [7:0] command;
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logic [31:0] arg [0:1];
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logic [31:0] response;
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logic boot_write;
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logic sdram_switch;
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logic sdram_writable;
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logic dd_enabled;
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logic sram_enabled;
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logic flashram_enabled;
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logic flashram_read_mode;
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logic [25:0] dd_offset;
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logic [25:0] save_offset;
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modport pi (
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input sdram_switch,
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input sdram_writable,
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input dd_enabled,
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input sram_enabled,
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input flashram_enabled,
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input flashram_read_mode,
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input dd_offset,
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input save_offset
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);
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modport flashram (
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output flashram_read_mode
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);
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modport n64 (
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input cpu_bootstrapped,
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input cpu_busy,
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output request,
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output command,
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output arg,
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input response,
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output boot_write
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);
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modport cpu (
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output cpu_bootstrapped,
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output cpu_busy,
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input request,
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input command,
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input arg,
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output response,
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input boot_write,
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output sdram_switch,
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output sdram_writable,
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output dd_enabled,
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output sram_enabled,
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output flashram_enabled,
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output dd_offset,
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output save_offset
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);
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endinterface
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