mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 06:19:16 +01:00
132 lines
2.8 KiB
Systemverilog
132 lines
2.8 KiB
Systemverilog
module SummerCart64 (
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input i_clk,
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input i_n64_reset,
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input i_n64_nmi,
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output o_n64_irq,
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input i_n64_pi_alel,
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input i_n64_pi_aleh,
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input i_n64_pi_read,
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input i_n64_pi_write,
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inout [15:0] io_n64_pi_ad,
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input i_n64_si_clk,
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inout io_n64_si_dq,
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output o_sdram_clk,
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output o_sdram_cs,
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output o_sdram_ras,
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output o_sdram_cas,
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output o_sdram_we,
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output [1:0] o_sdram_ba,
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output [12:0] o_sdram_a,
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inout [15:0] io_sdram_dq,
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output o_rtc_scl,
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inout io_rtc_sda,
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output o_usb_clk,
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output o_usb_cs,
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input i_usb_miso,
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inout [3:0] io_usb_miosi,
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input i_usb_pwren,
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input i_uart_rxd,
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output o_uart_txd,
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input i_uart_cts,
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output o_uart_rts,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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output o_led
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);
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logic [7:0] gpio_o;
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logic [7:0] gpio_i;
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logic [7:0] gpio_oe;
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if_system sys (
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.in_clk(i_clk),
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.n64_reset(i_n64_reset),
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.n64_nmi(i_n64_nmi)
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);
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if_config cfg ();
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if_dma dma ();
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system system_inst (
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.sys(sys)
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);
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intel_gpio_ddro sdram_clk_ddro (
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.outclock(sys.sdram.sdram_clk),
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.din({1'b0, 1'b1}),
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.pad_out(o_sdram_clk)
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);
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n64_soc n64_soc_inst (
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.sys(sys),
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.cfg(cfg),
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.dma(dma),
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.n64_pi_alel(i_n64_pi_alel),
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.n64_pi_aleh(i_n64_pi_aleh),
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.n64_pi_read(i_n64_pi_read),
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.n64_pi_write(i_n64_pi_write),
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.n64_pi_ad(io_n64_pi_ad),
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.n64_si_clk(i_n64_si_clk),
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.n64_si_dq(io_n64_si_dq),
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.sdram_cs(o_sdram_cs),
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.sdram_ras(o_sdram_ras),
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.sdram_cas(o_sdram_cas),
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.sdram_we(o_sdram_we),
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.sdram_ba(o_sdram_ba),
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.sdram_a(o_sdram_a),
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.sdram_dq(io_sdram_dq)
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);
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cpu_soc cpu_soc_inst (
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.sys(sys),
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.cfg(cfg),
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.dma(dma),
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.gpio_o(gpio_o),
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.gpio_i(gpio_i),
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.gpio_oe(gpio_oe),
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.i2c_scl(o_rtc_scl),
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.i2c_sda(io_rtc_sda),
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.usb_clk(o_usb_clk),
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.usb_cs(o_usb_cs),
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.usb_miso(i_usb_miso),
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.usb_miosi(io_usb_miosi),
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.usb_pwren(i_usb_pwren),
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.uart_rxd(i_uart_rxd),
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.uart_txd(o_uart_txd),
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.uart_cts(i_uart_cts),
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.uart_rts(o_uart_rts),
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.sd_clk(o_sd_clk),
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.sd_cmd(io_sd_cmd),
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.sd_dat(io_sd_dat)
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);
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always_comb begin
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o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ;
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o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ;
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end
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always_ff @(posedge sys.clk) begin
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gpio_i <= {4'b0000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
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end
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endmodule
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