mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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ff69030643
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec7.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
27 lines
899 B
Systemverilog
27 lines
899 B
Systemverilog
module fifo_junction (
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fifo_bus.controller dev_bus,
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fifo_bus.fifo cfg_bus,
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fifo_bus.fifo dma_bus
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);
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always_comb begin
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dev_bus.rx_read = cfg_bus.rx_read || dma_bus.rx_read;
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dev_bus.tx_write = cfg_bus.tx_write || dma_bus.tx_write;
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dev_bus.tx_wdata = cfg_bus.tx_write ? cfg_bus.tx_wdata : dma_bus.tx_wdata;
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cfg_bus.rx_empty = dev_bus.rx_empty;
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cfg_bus.rx_almost_empty = dev_bus.rx_almost_empty;
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cfg_bus.rx_rdata = dev_bus.rx_rdata;
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cfg_bus.tx_full = dev_bus.tx_full;
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cfg_bus.tx_almost_full = dev_bus.tx_almost_full;
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dma_bus.rx_empty = dev_bus.rx_empty;
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dma_bus.rx_almost_empty = dev_bus.rx_almost_empty;
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dma_bus.rx_rdata = dev_bus.rx_rdata;
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dma_bus.tx_full = dev_bus.tx_full;
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dma_bus.tx_almost_full = dev_bus.tx_almost_full;
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end
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endmodule
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