mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-24 06:39:14 +01:00
120 lines
2.1 KiB
Systemverilog
120 lines
2.1 KiB
Systemverilog
module n64_top (
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input clk,
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input reset,
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n64_scb n64_scb,
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dd_scb.dd dd_scb,
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mem_bus.controller mem_bus,
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input n64_reset,
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input n64_nmi,
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output n64_irq,
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input n64_pi_alel,
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input n64_pi_aleh,
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input n64_pi_read,
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input n64_pi_write,
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inout [15:0] n64_pi_ad,
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input n64_si_clk,
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inout n64_si_dq,
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input n64_cic_clk,
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inout n64_cic_dq
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);
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logic n64_dd_irq;
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logic n64_cfg_irq;
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logic n64_irq_oe;
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always @(posedge clk) begin
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n64_irq_oe <= (n64_dd_irq || n64_cfg_irq);
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end
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assign n64_irq = n64_irq_oe ? 1'b0 : 1'bZ;
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n64_reg_bus reg_bus ();
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n64_pi n64_pi_inst (
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.clk(clk),
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.reset(reset),
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.mem_bus(mem_bus),
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.reg_bus(reg_bus),
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.n64_scb(n64_scb),
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.n64_reset(n64_reset),
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.n64_nmi(n64_nmi),
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.n64_pi_alel(n64_pi_alel),
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.n64_pi_aleh(n64_pi_aleh),
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.n64_pi_read(n64_pi_read),
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.n64_pi_write(n64_pi_write),
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.n64_pi_ad(n64_pi_ad)
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);
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n64_dd n64_dd_inst (
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.clk(clk),
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.reset(reset),
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.reg_bus(reg_bus),
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.n64_scb(n64_scb),
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.dd_scb(dd_scb),
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.irq(n64_dd_irq)
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);
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n64_flashram n64_flashram_inst (
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.clk(clk),
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.reset(reset),
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.reg_bus(reg_bus),
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.n64_scb(n64_scb)
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);
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n64_cfg n64_cfg_inst (
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.clk(clk),
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.reset(reset),
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.reg_bus(reg_bus),
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.n64_scb(n64_scb),
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.irq(n64_cfg_irq)
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);
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n64_si n64_si_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb),
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.n64_reset(n64_reset),
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.n64_si_clk(n64_si_clk),
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.n64_si_dq(n64_si_dq)
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);
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n64_save_counter n64_save_counter_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb)
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);
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n64_cic n64_cic_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb),
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.n64_reset(n64_reset),
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.n64_cic_clk(n64_cic_clk),
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.n64_cic_dq(n64_cic_dq),
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.n64_si_clk(n64_si_clk)
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);
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endmodule
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