mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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235 lines
8.4 KiB
Verilog
Vendored
235 lines
8.4 KiB
Verilog
Vendored
/* Copyright lowRISC contributors.
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Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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Licensed under the Apache License, Version 2.0, see LICENSE for details.
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SPDX-License-Identifier: Apache-2.0
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* Adapted to SERV by @Abdulwadoodd as part of the project under spring '22 LFX Mentorship program */
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/* Decodes RISC-V compressed instructions into their RV32i equivalent. */
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module serv_compdec
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(
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input wire i_clk,
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input wire [31:0] i_instr,
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input wire i_ack,
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output wire [31:0] o_instr,
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output reg o_iscomp);
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localparam OPCODE_LOAD = 7'h03;
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localparam OPCODE_OP_IMM = 7'h13;
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localparam OPCODE_STORE = 7'h23;
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localparam OPCODE_OP = 7'h33;
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localparam OPCODE_LUI = 7'h37;
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localparam OPCODE_BRANCH = 7'h63;
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localparam OPCODE_JALR = 7'h67;
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localparam OPCODE_JAL = 7'h6f;
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reg [31:0] comp_instr;
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reg illegal_instr;
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assign o_instr = illegal_instr ? i_instr : comp_instr;
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always @(posedge i_clk) begin
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if(i_ack)
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o_iscomp <= !illegal_instr;
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end
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always @ (*) begin
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// By default, forward incoming instruction, mark it as legal.
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comp_instr = i_instr;
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illegal_instr = 1'b0;
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// Check if incoming instruction is compressed.
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case (i_instr[1:0])
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// C0
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2'b00: begin
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case (i_instr[15:14])
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2'b00: begin
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// c.addi4spn -> addi rd', x2, imm
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comp_instr = {2'b0, i_instr[10:7], i_instr[12:11], i_instr[5],
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i_instr[6], 2'b00, 5'h02, 3'b000, 2'b01, i_instr[4:2], {OPCODE_OP_IMM}};
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end
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2'b01: begin
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// c.lw -> lw rd', imm(rs1')
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comp_instr = {5'b0, i_instr[5], i_instr[12:10], i_instr[6],
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2'b00, 2'b01, i_instr[9:7], 3'b010, 2'b01, i_instr[4:2], {OPCODE_LOAD}};
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end
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2'b11: begin
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// c.sw -> sw rs2', imm(rs1')
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comp_instr = {5'b0, i_instr[5], i_instr[12], 2'b01, i_instr[4:2],
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2'b01, i_instr[9:7], 3'b010, i_instr[11:10], i_instr[6],
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2'b00, {OPCODE_STORE}};
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end
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2'b10: begin
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illegal_instr = 1'b1;
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end
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endcase
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end
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// C1
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// Register address checks for RV32E are performed in the regular instruction decoder.
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// If this check fails, an illegal instruction exception is triggered and the controller
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// writes the actual faulting instruction to mtval.
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2'b01: begin
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case (i_instr[15:13])
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3'b000: begin
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// c.addi -> addi rd, rd, nzimm
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// c.nop
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comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2],
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i_instr[11:7], 3'b0, i_instr[11:7], {OPCODE_OP_IMM}};
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end
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3'b001, 3'b101: begin
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// 001: c.jal -> jal x1, imm
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// 101: c.j -> jal x0, imm
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comp_instr = {i_instr[12], i_instr[8], i_instr[10:9], i_instr[6],
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i_instr[7], i_instr[2], i_instr[11], i_instr[5:3],
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{9 {i_instr[12]}}, 4'b0, ~i_instr[15], {OPCODE_JAL}};
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end
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3'b010: begin
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// c.li -> addi rd, x0, nzimm
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// (c.li hints are translated into an addi hint)
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comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2], 5'b0,
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3'b0, i_instr[11:7], {OPCODE_OP_IMM}};
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end
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3'b011: begin
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// c.lui -> lui rd, imm
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// (c.lui hints are translated into a lui hint)
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comp_instr = {{15 {i_instr[12]}}, i_instr[6:2], i_instr[11:7], {OPCODE_LUI}};
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if (i_instr[11:7] == 5'h02) begin
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// c.addi16sp -> addi x2, x2, nzimm
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comp_instr = {{3 {i_instr[12]}}, i_instr[4:3], i_instr[5], i_instr[2],
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i_instr[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}};
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end
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end
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3'b100: begin
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case (i_instr[11:10])
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2'b00,
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2'b01: begin
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// 00: c.srli -> srli rd, rd, shamt
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// 01: c.srai -> srai rd, rd, shamt
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// (c.srli/c.srai hints are translated into a srli/srai hint)
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comp_instr = {1'b0, i_instr[10], 5'b0, i_instr[6:2], 2'b01, i_instr[9:7],
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3'b101, 2'b01, i_instr[9:7], {OPCODE_OP_IMM}};
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end
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2'b10: begin
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// c.andi -> andi rd, rd, imm
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comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2], 2'b01, i_instr[9:7],
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3'b111, 2'b01, i_instr[9:7], {OPCODE_OP_IMM}};
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end
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2'b11: begin
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case (i_instr[6:5])
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2'b00: begin
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// c.sub -> sub rd', rd', rs2'
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comp_instr = {2'b01, 5'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7],
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3'b000, 2'b01, i_instr[9:7], {OPCODE_OP}};
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end
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2'b01: begin
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// c.xor -> xor rd', rd', rs2'
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comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b100,
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2'b01, i_instr[9:7], {OPCODE_OP}};
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end
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2'b10: begin
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// c.or -> or rd', rd', rs2'
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comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b110,
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2'b01, i_instr[9:7], {OPCODE_OP}};
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end
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2'b11: begin
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// c.and -> and rd', rd', rs2'
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comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b111,
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2'b01, i_instr[9:7], {OPCODE_OP}};
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end
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endcase
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end
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endcase
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end
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3'b110, 3'b111: begin
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// 0: c.beqz -> beq rs1', x0, imm
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// 1: c.bnez -> bne rs1', x0, imm
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comp_instr = {{4 {i_instr[12]}}, i_instr[6:5], i_instr[2], 5'b0, 2'b01,
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i_instr[9:7], 2'b00, i_instr[13], i_instr[11:10], i_instr[4:3],
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i_instr[12], {OPCODE_BRANCH}};
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end
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endcase
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end
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// C2
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// Register address checks for RV32E are performed in the regular instruction decoder.
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// If this check fails, an illegal instruction exception is triggered and the controller
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// writes the actual faulting instruction to mtval.
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2'b10: begin
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case (i_instr[15:14])
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2'b00: begin
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// c.slli -> slli rd, rd, shamt
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// (c.ssli hints are translated into a slli hint)
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comp_instr = {7'b0, i_instr[6:2], i_instr[11:7], 3'b001, i_instr[11:7], {OPCODE_OP_IMM}};
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end
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2'b01: begin
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// c.lwsp -> lw rd, imm(x2)
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comp_instr = {4'b0, i_instr[3:2], i_instr[12], i_instr[6:4], 2'b00, 5'h02,
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3'b010, i_instr[11:7], OPCODE_LOAD};
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end
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2'b10: begin
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if (i_instr[12] == 1'b0) begin
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if (i_instr[6:2] != 5'b0) begin
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// c.mv -> add rd/rs1, x0, rs2
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// (c.mv hints are translated into an add hint)
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comp_instr = {7'b0, i_instr[6:2], 5'b0, 3'b0, i_instr[11:7], {OPCODE_OP}};
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end else begin
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// c.jr -> jalr x0, rd/rs1, 0
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comp_instr = {12'b0, i_instr[11:7], 3'b0, 5'b0, {OPCODE_JALR}};
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end
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end else begin
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if (i_instr[6:2] != 5'b0) begin
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// c.add -> add rd, rd, rs2
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// (c.add hints are translated into an add hint)
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comp_instr = {7'b0, i_instr[6:2], i_instr[11:7], 3'b0, i_instr[11:7], {OPCODE_OP}};
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end else begin
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if (i_instr[11:7] == 5'b0) begin
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// c.ebreak -> ebreak
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comp_instr = {32'h00_10_00_73};
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end else begin
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// c.jalr -> jalr x1, rs1, 0
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comp_instr = {12'b0, i_instr[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};
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end
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end
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end
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end
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2'b11: begin
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// c.swsp -> sw rs2, imm(x2)
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comp_instr = {4'b0, i_instr[8:7], i_instr[12], i_instr[6:2], 5'h02, 3'b010,
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i_instr[11:9], 2'b00, {OPCODE_STORE}};
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end
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endcase
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end
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// Incoming instruction is not compressed.
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2'b11: illegal_instr = 1'b1;
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endcase
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end
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endmodule
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