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29 lines
520 B
Systemverilog
29 lines
520 B
Systemverilog
module sd_crc_7 (
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input clk,
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input reset,
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input enable,
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input data,
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output logic [6:0] result
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);
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logic crc_inv;
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assign crc_inv = result[6] ^ data;
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always_ff @(posedge clk) begin
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if (reset) begin
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result <= 7'd0;
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end else if (enable) begin
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result <= {
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result[5:3],
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result[2] ^ crc_inv,
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result[1:0],
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crc_inv
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};
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end
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end
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endmodule
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