Polprzewodnikowy ccaa4a815e cpu buffer		2022-01-20 20:28:59 +01:00
..
cpu_bus.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_cfg.sv	[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)	2021-12-10 17:36:30 +01:00
cpu_dd.sv	[SC64][FW][SW] Added 64DD implementation with USB streaming (#14)	2021-12-24 23:51:30 +01:00
cpu_dma.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_flash.sv	[SC64][FW][SW] Load CPU software directly from embedded flash in FPGA (#9)	2021-10-26 23:44:09 +02:00
cpu_flashram.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_gpio.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_i2c.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_ram.sv	cpu buffer	2022-01-20 20:28:59 +01:00
cpu_sdram.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_si.sv	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00
cpu_soc.sv	cpu buffer	2022-01-20 20:28:59 +01:00
cpu_uart.sv	[SC64][FW][SW] Updated project for Quartus Lite 21.1, reworked build script, minor fixes in USB and CFG modules (#11)	2021-11-10 02:05:51 +01:00
cpu_usb.sv	[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)	2021-12-10 17:36:30 +01:00
cpu_wrapper.sv	[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)	2021-11-16 22:37:48 +01:00