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50 lines
1.2 KiB
Systemverilog
50 lines
1.2 KiB
Systemverilog
module fifo_mock #(
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parameter int DEPTH = 1024,
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localparam int PTR_BITS = $clog2(DEPTH)
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) (
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input clk,
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input reset,
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output logic empty,
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input read,
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output [7:0] rdata,
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output logic full,
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input write,
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input [7:0] wdata,
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output logic [PTR_BITS:0] count
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);
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logic [7:0] fifo_mem [0:(DEPTH - 1)];
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logic [(PTR_BITS - 1):0] fifo_rptr;
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logic [(PTR_BITS - 1):0] fifo_wptr;
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always_comb begin
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full = count >= (PTR_BITS + 1)'(DEPTH);
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empty = count == (PTR_BITS + 1)'('d0);
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end
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always_ff @(posedge clk) begin
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if (read) begin
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rdata <= fifo_mem[fifo_rptr];
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fifo_rptr <= fifo_rptr + PTR_BITS'('d1);
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count <= count - (PTR_BITS + 1)'('d1);
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end
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if (write) begin
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fifo_mem[fifo_wptr] <= wdata;
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fifo_wptr <= fifo_wptr + PTR_BITS'('d1);
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count <= count + (PTR_BITS + 1)'('d1);
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end
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if (read && write) begin
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count <= count;
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end
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if (reset) begin
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count <= (PTR_BITS + 1)'('d0);
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fifo_rptr <= PTR_BITS'('d0);
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fifo_wptr <= PTR_BITS'('d0);
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end
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end
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endmodule
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