mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 14:09:16 +01:00
217 lines
6.4 KiB
Verilog
Vendored
217 lines
6.4 KiB
Verilog
Vendored
`default_nettype none
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module serv_rf_top
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#(parameter RESET_PC = 32'd0,
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/* COMPRESSED=1: Enable the compressed decoder and allowed misaligned jump of pc
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COMPRESSED=0: Disable the compressed decoder and does not allow the misaligned jump of pc
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*/
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parameter [0:0] COMPRESSED = 0,
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/*
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ALIGN = 1: Fetch the aligned instruction by making two bus transactions if the misaligned address
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is given to the instruction bus.
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*/
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parameter [0:0] ALIGN = COMPRESSED,
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/* Multiplication and Division Unit
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This parameter enables the interface for connecting SERV and MDU
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*/
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parameter [0:0] MDU = 0,
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/* Register signals before or after the decoder
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0 : Register after the decoder. Faster but uses more resources
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1 : (default) Register before the decoder. Slower but uses less resources
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*/
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parameter PRE_REGISTER = 1,
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/* Amount of reset applied to design
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"NONE" : No reset at all. Relies on a POR to set correct initialization
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values and that core isn't reset during runtime
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"MINI" : Standard setting. Resets the minimal amount of FFs needed to
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restart execution from the instruction at RESET_PC
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*/
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parameter RESET_STRATEGY = "MINI",
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parameter WITH_CSR = 1,
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parameter RF_WIDTH = 2,
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parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
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(
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input wire clk,
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input wire i_rst,
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input wire i_timer_irq,
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`ifdef RISCV_FORMAL
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output wire rvfi_valid,
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output wire [63:0] rvfi_order,
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output wire [31:0] rvfi_insn,
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output wire rvfi_trap,
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output wire rvfi_halt,
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output wire rvfi_intr,
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output wire [1:0] rvfi_mode,
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output wire [1:0] rvfi_ixl,
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output wire [4:0] rvfi_rs1_addr,
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output wire [4:0] rvfi_rs2_addr,
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output wire [31:0] rvfi_rs1_rdata,
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output wire [31:0] rvfi_rs2_rdata,
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output wire [4:0] rvfi_rd_addr,
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output wire [31:0] rvfi_rd_wdata,
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output wire [31:0] rvfi_pc_rdata,
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output wire [31:0] rvfi_pc_wdata,
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output wire [31:0] rvfi_mem_addr,
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output wire [3:0] rvfi_mem_rmask,
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output wire [3:0] rvfi_mem_wmask,
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output wire [31:0] rvfi_mem_rdata,
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output wire [31:0] rvfi_mem_wdata,
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`endif
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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output wire [31:0] o_dbus_adr,
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output wire [31:0] o_dbus_dat,
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output wire [3:0] o_dbus_sel,
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output wire o_dbus_we ,
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output wire o_dbus_cyc,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack,
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// Extension
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output wire [31:0] o_ext_rs1,
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output wire [31:0] o_ext_rs2,
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output wire [ 2:0] o_ext_funct3,
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input wire [31:0] i_ext_rd,
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input wire i_ext_ready,
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// MDU
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output wire o_mdu_valid);
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localparam CSR_REGS = WITH_CSR*4;
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wire rf_wreq;
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wire rf_rreq;
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wire [4+WITH_CSR:0] wreg0;
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wire [4+WITH_CSR:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [4+WITH_CSR:0] rreg0;
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wire [4+WITH_CSR:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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wire [RF_L2D-1:0] waddr;
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wire [RF_WIDTH-1:0] wdata;
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wire wen;
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wire [RF_L2D-1:0] raddr;
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wire ren;
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wire [RF_WIDTH-1:0] rdata;
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serv_rf_ram_if
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#(.width (RF_WIDTH),
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.reset_strategy (RESET_STRATEGY),
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.csr_regs (CSR_REGS))
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rf_ram_if
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(.i_clk (clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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.i_rreq (rf_rreq),
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.o_ready (rf_ready),
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.i_wreg0 (wreg0),
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.i_wreg1 (wreg1),
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.i_wen0 (wen0),
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.i_wen1 (wen1),
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.i_wdata0 (wdata0),
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.i_wdata1 (wdata1),
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1),
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.o_waddr (waddr),
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.o_wdata (wdata),
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.o_wen (wen),
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.o_raddr (raddr),
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.o_ren (ren),
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.i_rdata (rdata));
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serv_rf_ram
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#(.width (RF_WIDTH),
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.csr_regs (CSR_REGS))
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rf_ram
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(.i_clk (clk),
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.i_waddr (waddr),
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.i_wdata (wdata),
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.i_wen (wen),
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.i_raddr (raddr),
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.i_ren (ren),
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.o_rdata (rdata));
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serv_top
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#(.RESET_PC (RESET_PC),
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.PRE_REGISTER (PRE_REGISTER),
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.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR),
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.MDU(MDU),
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.COMPRESSED(COMPRESSED),
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.ALIGN(ALIGN))
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cpu
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_timer_irq (i_timer_irq),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_mode (rvfi_mode ),
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.rvfi_ixl (rvfi_ixl ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata),
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.rvfi_rs2_rdata (rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask),
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.rvfi_mem_wmask (rvfi_mem_wmask),
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.rvfi_mem_rdata (rvfi_mem_rdata),
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.rvfi_mem_wdata (rvfi_mem_wdata),
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`endif
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.o_wreg0 (wreg0),
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.o_wreg1 (wreg1),
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.o_wen0 (wen0),
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.o_wen1 (wen1),
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.o_wdata0 (wdata0),
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.o_wdata1 (wdata1),
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.o_rreg0 (rreg0),
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.o_rreg1 (rreg1),
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.i_rdata0 (rdata0),
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.i_rdata1 (rdata1),
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.o_ibus_adr (o_ibus_adr),
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_rdt (i_ibus_rdt),
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.i_ibus_ack (i_ibus_ack),
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.o_dbus_adr (o_dbus_adr),
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.o_dbus_dat (o_dbus_dat),
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.o_dbus_sel (o_dbus_sel),
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.o_dbus_we (o_dbus_we),
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.o_dbus_cyc (o_dbus_cyc),
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.i_dbus_rdt (i_dbus_rdt),
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.i_dbus_ack (i_dbus_ack),
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//Extension
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.o_ext_funct3 (o_ext_funct3),
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.i_ext_ready (i_ext_ready),
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.i_ext_rd (i_ext_rd),
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.o_ext_rs1 (o_ext_rs1),
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.o_ext_rs2 (o_ext_rs2),
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//MDU
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.o_mdu_valid (o_mdu_valid));
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endmodule
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`default_nettype wire
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