Mateusz Faderewski 1b71b4a333 [SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)		2024-07-21 11:15:08 +02:00
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generated	[SC64][FW] Set timing constraints for SDRAM pins	2024-05-05 07:08:44 +02:00
fifo_8kb.sv	[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)	2024-07-21 11:15:08 +02:00
pll.sv	[SC64][FW] Set timing constraints for SDRAM pins	2024-05-05 07:08:44 +02:00
vendor.sv	[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)	2022-11-10 11:46:54 +01:00