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35 lines
744 B
Verilog
35 lines
744 B
Verilog
module sd_dma (
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input i_clk,
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input i_reset,
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input [3:0] i_dma_bank,
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input [23:0] i_dma_address,
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input [14:0] i_dma_length,
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output reg [14:0] o_dma_left,
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input i_dma_load_bank_address,
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input i_dma_load_length,
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input i_dma_direction,
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input i_dma_start,
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input i_dma_stop,
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output reg o_dma_busy,
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output reg o_rx_fifo_pop,
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input i_rx_fifo_empty,
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input [31:0] i_rx_fifo_data,
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output reg o_tx_fifo_push,
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input i_tx_fifo_full,
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output reg [31:0] o_tx_fifo_data,
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output reg o_request,
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output reg o_write,
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input i_busy,
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input i_ack,
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output reg [3:0] o_bank,
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output reg [23:0] o_address,
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input [31:0] i_data,
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output reg [31:0] o_data
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);
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endmodule
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