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https://github.com/Polprzewodnikowy/SummerCart64.git
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146 lines
3.4 KiB
Systemverilog
146 lines
3.4 KiB
Systemverilog
module fifo_bus_fifo_mock #(
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parameter int DEPTH = 1024,
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parameter int FILL_RATE = 3,
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parameter int DRAIN_RATE = 3
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) (
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input clk,
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input reset,
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fifo_bus.fifo fifo_bus,
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input flush,
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input rx_fill_enabled,
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input tx_drain_enabled
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);
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localparam int PTR_BITS = $clog2(DEPTH);
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// RX FIFO mock
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logic rx_full;
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logic rx_write;
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logic [7:0] rx_wdata;
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logic [PTR_BITS:0] rx_count;
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fifo_mock #(
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.DEPTH(DEPTH)
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) fifo_rx (
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.clk(clk),
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.reset(reset),
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.empty(fifo_bus.rx_empty),
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.read(fifo_bus.rx_read),
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.rdata(fifo_bus.rx_rdata),
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.full(rx_full),
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.write(rx_write),
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.wdata(rx_wdata),
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.count(rx_count)
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);
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localparam int FILL_BITS = $clog2(FILL_RATE);
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logic [FILL_BITS:0] fill_counter;
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logic rx_fill;
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always_ff @(posedge clk) begin
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rx_fill <= rx_fill_enabled;
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end
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generate;
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if (FILL_RATE == 0) begin
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always_comb begin
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rx_write = rx_fill && !rx_full;
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end
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end else begin
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always_comb begin
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rx_write = rx_fill && !rx_full && (fill_counter == (FILL_BITS + 1)'(FILL_RATE));
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end
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always_ff @(posedge clk) begin
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if (fill_counter < (FILL_BITS + 1)'(FILL_RATE)) begin
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fill_counter <= fill_counter + (FILL_BITS + 1)'('d1);
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end
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if (reset) begin
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fill_counter <= (FILL_BITS + 1)'('d0);
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end else begin
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if (rx_write) begin
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fill_counter <= (FILL_BITS + 1)'('d0);
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end
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end
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end
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end
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endgenerate
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always_ff @(posedge clk) begin
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if (reset) begin
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rx_wdata <= 8'h01;
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end else begin
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if (rx_write) begin
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rx_wdata <= rx_wdata + 8'h01;
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end
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end
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end
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// TX FIFO mock
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logic tx_empty;
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logic tx_read;
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logic [7:0] tx_rdata;
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logic [PTR_BITS:0] tx_count;
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fifo_mock #(
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.DEPTH(DEPTH)
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) fifo_tx (
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.clk(clk),
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.reset(reset),
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.empty(tx_empty),
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.read(tx_read),
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.rdata(tx_rdata),
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.full(fifo_bus.tx_full),
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.write(fifo_bus.tx_write),
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.wdata(fifo_bus.tx_wdata),
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.count(tx_count)
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);
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localparam int DRAIN_BITS = $clog2(DRAIN_RATE);
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logic [DRAIN_BITS:0] drain_counter;
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logic tx_drain;
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always_ff @(posedge clk) begin
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tx_drain <= tx_drain_enabled;
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end
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generate;
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if (DRAIN_RATE == 0) begin
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always_comb begin
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tx_read = tx_drain && !tx_empty;
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end
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end else begin
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always_comb begin
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tx_read = tx_drain && !tx_empty && (drain_counter == (DRAIN_BITS + 1)'(DRAIN_RATE));
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end
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always_ff @(posedge clk) begin
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if (drain_counter < (DRAIN_BITS + 1)'(DRAIN_RATE)) begin
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drain_counter <= drain_counter + (DRAIN_BITS + 1)'('d1);
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end
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if (reset) begin
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drain_counter <= (DRAIN_BITS + 1)'('d0);
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end else begin
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if (tx_read) begin
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drain_counter <= (DRAIN_BITS + 1)'('d0);
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end
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end
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end
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end
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endgenerate
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endmodule
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