mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-27 08:04:14 +01:00
310 lines
8.6 KiB
Verilog
310 lines
8.6 KiB
Verilog
module sd_interface (
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input i_clk,
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input i_reset,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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input i_request,
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input i_write,
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output o_busy,
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output o_ack,
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input [3:0] i_address,
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output [31:0] o_data,
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input [31:0] i_data,
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output o_dma_request,
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output o_dma_write,
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input i_dma_busy,
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input i_dma_ack,
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output [3:0] o_dma_bank,
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output [23:0] o_dma_address,
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input [31:0] i_dma_data,
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output [31:0] o_dma_data
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);
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// Clock generator
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wire [1:0] w_sd_clk_config;
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wire w_sd_clk_strobe_rising;
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wire w_sd_clk_strobe_falling;
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sd_clk sd_clk_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.i_sd_clk_config(w_sd_clk_config),
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.o_sd_clk_strobe_rising(w_sd_clk_strobe_rising),
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.o_sd_clk_strobe_falling(w_sd_clk_strobe_falling),
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.o_sd_clk(o_sd_clk)
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);
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// Command path
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wire [5:0] w_command_index;
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wire [31:0] w_command_argument;
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wire w_command_skip_response;
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wire w_command_long_response;
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wire [5:0] w_command_response_index;
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wire [31:0] w_command_response;
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wire w_command_start;
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wire w_command_busy;
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wire w_command_timeout;
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wire w_command_response_crc_error;
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sd_cmd sd_cmd_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.io_sd_cmd(io_sd_cmd),
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.i_sd_clk_strobe_rising(w_sd_clk_strobe_rising),
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.i_sd_clk_strobe_falling(w_sd_clk_strobe_falling),
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.i_command_index(w_command_index),
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.i_command_argument(w_command_argument),
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.i_command_long_response(w_command_long_response),
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.i_command_skip_response(w_command_skip_response),
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.o_command_index(w_command_response_index),
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.o_command_response(w_command_response),
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.i_command_start(w_command_start),
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.o_command_busy(w_command_busy),
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.o_command_timeout(w_command_timeout),
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.o_command_response_crc_error(w_command_response_crc_error)
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);
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// SD to FPGA (RX) data path FIFO
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wire w_rx_fifo_flush;
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wire w_rx_fifo_push;
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wire w_rx_fifo_regs_pop;
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wire w_rx_fifo_dma_pop;
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wire w_rx_fifo_empty;
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wire w_rx_fifo_full;
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wire w_rx_fifo_overrun;
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wire [8:0] w_rx_fifo_items;
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wire [31:0] w_rx_fifo_i_data;
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wire [31:0] w_rx_fifo_o_data;
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sd_fifo sd_fifo_rx_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.i_fifo_flush(w_rx_fifo_flush),
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.i_fifo_push(w_rx_fifo_push),
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.i_fifo_pop(w_rx_fifo_regs_pop || w_rx_fifo_dma_pop),
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.o_fifo_empty(w_rx_fifo_empty),
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.o_fifo_full(w_rx_fifo_full),
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.o_fifo_underrun(),
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.o_fifo_overrun(w_rx_fifo_overrun),
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.o_fifo_items(w_rx_fifo_items),
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.i_fifo_data(w_rx_fifo_i_data),
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.o_fifo_data(w_rx_fifo_o_data)
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);
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// FPGA to SD (TX) data path FIFO
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wire w_tx_fifo_flush;
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wire w_tx_fifo_regs_push;
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wire w_tx_fifo_dma_push;
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wire w_tx_fifo_pop;
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wire w_tx_fifo_empty;
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wire w_tx_fifo_full;
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wire w_tx_fifo_underrun;
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wire [8:0] w_tx_fifo_items;
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reg [31:0] r_tx_fifo_i_data;
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wire [31:0] w_tx_fifo_o_data;
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wire [31:0] w_tx_fifo_i_data_regs;
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wire [31:0] w_tx_fifo_i_data_dma;
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always @(*) begin
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r_tx_fifo_i_data = 32'h0000_0000;
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if (w_tx_fifo_regs_push) r_tx_fifo_i_data = w_tx_fifo_i_data_regs;
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if (w_tx_fifo_dma_push) r_tx_fifo_i_data = w_tx_fifo_i_data_dma;
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end
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sd_fifo sd_fifo_tx_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.i_fifo_flush(w_tx_fifo_flush),
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.i_fifo_push(w_tx_fifo_regs_push || w_tx_fifo_dma_push),
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.i_fifo_pop(w_tx_fifo_pop),
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.o_fifo_empty(w_tx_fifo_empty),
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.o_fifo_full(w_tx_fifo_full),
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.o_fifo_underrun(w_tx_fifo_underrun),
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.o_fifo_overrun(),
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.o_fifo_items(w_tx_fifo_items),
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.i_fifo_data(r_tx_fifo_i_data),
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.o_fifo_data(w_tx_fifo_o_data)
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);
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// Data path
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wire w_dat_width;
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wire w_dat_direction;
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wire [6:0] w_dat_block_size;
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wire [7:0] w_dat_num_blocks;
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wire w_dat_start;
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wire w_dat_stop;
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wire w_dat_busy;
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wire w_dat_write_busy;
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wire w_dat_crc_error;
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wire w_dat_write_error;
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sd_dat sd_dat_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.io_sd_dat(io_sd_dat),
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.i_sd_clk_strobe_rising(w_sd_clk_strobe_rising),
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.i_sd_clk_strobe_falling(w_sd_clk_strobe_falling),
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.i_dat_width(w_dat_width),
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.i_dat_direction(w_dat_direction),
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.i_dat_block_size(w_dat_block_size),
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.i_dat_num_blocks(w_dat_num_blocks),
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.i_dat_start(w_dat_start),
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.i_dat_stop(w_dat_stop),
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.o_dat_busy(w_dat_busy),
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.o_dat_write_busy(w_dat_write_busy),
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.o_dat_crc_error(w_dat_crc_error),
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.o_dat_write_error(w_dat_write_error),
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.i_rx_fifo_overrun(w_rx_fifo_overrun),
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.o_rx_fifo_push(w_rx_fifo_push),
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.o_rx_fifo_data(w_rx_fifo_i_data),
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.i_tx_fifo_items(w_tx_fifo_items),
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.i_tx_fifo_underrun(w_tx_fifo_underrun),
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.o_tx_fifo_pop(w_tx_fifo_pop),
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.i_tx_fifo_data(w_tx_fifo_o_data)
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);
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// DMA
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wire [3:0] w_dma_bank;
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wire [23:0] w_dma_address;
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wire [14:0] w_dma_length;
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wire [14:0] w_dma_left;
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wire w_dma_load_bank_address;
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wire w_dma_load_length;
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wire w_dma_direction;
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wire w_dma_start;
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wire w_dma_stop;
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wire w_dma_busy;
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sd_dma sd_dma_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.i_dma_bank(w_dma_bank),
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.i_dma_address(w_dma_address),
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.i_dma_length(w_dma_length),
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.o_dma_left(w_dma_left),
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.i_dma_load_bank_address(w_dma_load_bank_address),
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.i_dma_load_length(w_dma_load_length),
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.i_dma_direction(w_dma_direction),
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.i_dma_start(w_dma_start),
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.i_dma_stop(w_dma_stop),
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.o_dma_busy(w_dma_busy),
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.o_rx_fifo_pop(w_rx_fifo_dma_pop),
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.i_rx_fifo_empty(w_rx_fifo_empty),
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.i_rx_fifo_data(w_rx_fifo_o_data),
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.o_tx_fifo_push(w_tx_fifo_dma_push),
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.i_tx_fifo_full(w_tx_fifo_full),
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.o_tx_fifo_data(w_tx_fifo_i_data_dma),
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.o_request(o_dma_request),
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.o_write(o_dma_write),
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.i_busy(i_dma_busy),
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.i_ack(i_dma_ack),
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.o_bank(o_dma_bank),
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.o_address(o_dma_address),
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.i_data(i_dma_data),
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.o_data(o_dma_data)
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);
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// Peripheral registers
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sd_regs sd_regs_inst (
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.i_clk(i_clk),
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.i_reset(i_reset),
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.o_sd_clk_config(w_sd_clk_config),
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.o_command_index(w_command_index),
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.o_command_argument(w_command_argument),
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.o_command_long_response(w_command_long_response),
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.o_command_skip_response(w_command_skip_response),
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.i_command_index(w_command_response_index),
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.i_command_response(w_command_response),
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.o_command_start(w_command_start),
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.i_command_busy(w_command_busy),
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.i_command_timeout(w_command_timeout),
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.i_command_response_crc_error(w_command_response_crc_error),
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.o_dat_width(w_dat_width),
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.o_dat_direction(w_dat_direction),
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.o_dat_block_size(w_dat_block_size),
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.o_dat_num_blocks(w_dat_num_blocks),
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.o_dat_start(w_dat_start),
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.o_dat_stop(w_dat_stop),
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.i_dat_busy(w_dat_busy),
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.i_dat_write_busy(w_dat_write_busy),
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.i_dat_crc_error(w_dat_crc_error),
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.i_dat_write_error(w_dat_write_error),
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.o_rx_fifo_flush(w_rx_fifo_flush),
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.o_rx_fifo_pop(w_rx_fifo_regs_pop),
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.i_rx_fifo_empty(w_rx_fifo_empty),
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.i_rx_fifo_full(w_rx_fifo_full),
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.i_rx_fifo_overrun(w_rx_fifo_overrun),
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.i_rx_fifo_items(w_rx_fifo_items),
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.i_rx_fifo_data(w_rx_fifo_o_data),
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.o_tx_fifo_flush(w_tx_fifo_flush),
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.o_tx_fifo_push(w_tx_fifo_regs_push),
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.i_tx_fifo_empty(w_tx_fifo_empty),
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.i_tx_fifo_full(w_tx_fifo_full),
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.i_tx_fifo_underrun(w_tx_fifo_underrun),
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.i_tx_fifo_items(w_tx_fifo_items),
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.o_tx_fifo_data(w_tx_fifo_i_data_regs),
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.o_dma_bank(w_dma_bank),
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.o_dma_address(w_dma_address),
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.o_dma_length(w_dma_length),
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.i_dma_bank(o_dma_bank),
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.i_dma_address(o_dma_address),
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.i_dma_left(w_dma_left),
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.o_dma_load_bank_address(w_dma_load_bank_address),
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.o_dma_load_length(w_dma_load_length),
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.o_dma_direction(w_dma_direction),
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.o_dma_start(w_dma_start),
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.o_dma_stop(w_dma_stop),
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.i_dma_busy(w_dma_busy),
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.i_request(i_request),
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.i_write(i_write),
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.o_busy(o_busy),
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.o_ack(o_ack),
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.i_address(i_address),
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.o_data(o_data),
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.i_data(i_data)
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);
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endmodule
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