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25 lines
499 B
Systemverilog
25 lines
499 B
Systemverilog
module n64_save_counter (
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input clk,
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input reset,
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n64_scb.save_counter n64_scb
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);
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logic [15:0] counter;
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always_ff @(posedge clk) begin
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if (reset) begin
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counter <= 16'd0;
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end else begin
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if (n64_scb.eeprom_write || n64_scb.sram_done || n64_scb.flashram_done) begin
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counter <= counter + 1'd1;
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end
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end
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end
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always_ff @(posedge clk) begin
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n64_scb.save_count <= counter;
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end
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endmodule
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